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PDF UPD72850A Data sheet ( Hoja de datos )
| Número de pieza | UPD72850A | |
| Descripción | IEEE1394 400Mbps PHY | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD72850A
IEEE1394 400Mbps PHY
The µPD72850A is the 3-port physical layer LSI which complies with the P1394a draft 2.0 specifications.
The µPD72850A works up to 400 Mbps. It is an upgrade of NEC's µPD72850.
FEATURES
• The Three-port Physical Layer LSI complies to IEEE P1394a draft 2.0
• Connection debounce
• Arbitration enhancements
• Arbitrated short bus reset
• Ack-accelerated arbitration
• Fly-by concatenation
• Multiple-speed packet concatenation
• Arbitration enhancements and cycle start (controlled by the Link layer)
• Performance optimization via PHY pinging
• Priority arbitration (controlled by the Link layer)
• Data rate: 393.216 / 196.608 / 98.304 Mbps
• Compliant with Suspend/Resume function as defined in P1394a draft 2.1
• 3.3 V single power supply
• Electrical isolated Link interface
• 24.576 MHz crystal clock generation, 393.216 MHz PLL multiplying frequency
• System power management by signaling of node power class information
• Cable power monitor (CPS) is equipped
• Fully interoperable with IEEE1394 std 1394 Link (FireWireTM, i.LINKTM)
• Cable bias and terminal voltage driver supply function (for 3-port each)
• Separate digital power and analog GND
• Enable/Disable port control switch when power supply is powered on
• Support Suspend/Resume Off mode (Compliant with P1394a draft 1.3)
• Number of supported port are selectable
• 1port, 2port, 3port. This selection is only under Suspend/Resume Off mode
• Compliant with MD8405E (FUJIFILM MICRODEVICES CO., LTD)
ORDERING INFORMATION
Part number
Package
µPD72850AGK-9EU
80-pin plastic TQFP (Fine pitch) (12 x 12 mm)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14452EJ1V0DS00 (1st edition)
Date Published October 1999 NS CP(K)
Printed in Japan
1999
1 page  
µPD72850A
CONTENTS
1. PIN FUNCTIONS ..................................................................................................................................... 7
1.1 Cable Interface Pins......................................................................................................................... 7
1.2 Link Interface Pins ........................................................................................................................... 8
1.3 Control Pins...................................................................................................................................... 8
1.4 IC........................................................................................................................................................ 9
1.5 Power Supply Pins........................................................................................................................... 9
1.6 Other Pins......................................................................................................................................... 9
2. PHY REGISTERS ................................................................................................................................... 10
2.1 Complete Structure for PHY Registers ........................................................................................ 10
2.2 Port Status Page (Page 000) ......................................................................................................... 13
2.3 Vendor ID Page (Page 001) ........................................................................................................... 14
3. INTERNAL FUNCTION .......................................................................................................................... 15
3.1 Link Interface.................................................................................................................................. 15
3.1.1 Connection Method............................................................................................................................... 15
3.1.2 LPS (Link Power Status)....................................................................................................................... 15
3.1.3 LREQ, CTL0,CTL1, and D0-D7 Pins .................................................................................................... 15
3.1.4 SCLK..................................................................................................................................................... 15
3.1.5 LKON .................................................................................................................................................... 16
3.1.6 Direct .................................................................................................................................................... 16
3.1.7 Isolation Barrier..................................................................................................................................... 16
3.2 Cable Interface ............................................................................................................................... 18
3.2.1 Connections.......................................................................................................................................... 18
3.2.2 Cable Interface Circuit .......................................................................................................................... 19
3.2.3 Unused Ports ........................................................................................................................................ 19
3.2.4 CPS....................................................................................................................................................... 19
3.3 Suspend/Resume........................................................................................................................... 19
3.3.1 Suspend/Resume On Mode (SUS/RES = “H”)...................................................................................... 19
3.3.2 Suspend/Resume Off Mode (SUS/RES = “L”) ...................................................................................... 19
3.4 PLL and Crystal Oscillation Circuit.............................................................................................. 20
3.4.1 Crystal Oscillation Circuit...................................................................................................................... 20
3.4.2 PLL ....................................................................................................................................................... 20
3.5 PC0-PC2, CMC................................................................................................................................ 20
3.6 RESETB........................................................................................................................................... 20
3.7 RI1, RI0 ............................................................................................................................................ 20
4. PHY/LINK INTERFACE.......................................................................................................................... 21
4.1 Initialization of Link Power Status (LPS) and PHY/Link Interface............................................. 21
4.2 Link-on Indication .......................................................................................................................... 22
4.3 PHY/Link Interface Operation (CTL0, CTL1, LREQ, D0-D7) ....................................................... 23
4.3.1 CTL0,CTL1 ........................................................................................................................................... 23
4.3.2 LREQ .................................................................................................................................................... 23
4.3.3 PHY/Link Interface Timing .................................................................................................................... 27
4.4 Acceleration Control...................................................................................................................... 28
4.5 Transmit Status.............................................................................................................................. 29
Data Sheet S14452EJ1V0DS00
5
5 Page 
µPD72850A
Field
Physical_ID
R
PS
RHB
IBR
Gap_count
Extended
Total_ports
Max_speed
Delay
Link_active
Contender
Jitter
Table 2-1. Bit Field Description (1/2)
Size R/W Reset value
Description
6R
000000 Physical_ID value selected from Self_ID period.
1R
0 If this bit is 1, the node is root.
1: Root
0: Not root
1R
Cable power status.
1: Cable power on
0: Cable power off
1 R/W 0 Root Hold -off bit. If 1, becomes root at the bus reset.
1 R/W 0 Initiate bus reset.
Setting to 1 begins a long bus reset.
Long bus reset signal duration: 166 µsec.
Returns to 0 at the beginning of bus reset.
6 R/W
111111 Gap count value.
It is updated by the changes of transmitting and receiving the PHY
configuration packet Tx/Rx.
The value is maintained after first bus reset.
After the second bus reset it returns to reset value.
3R
111 Shows the extended register map.
4R
0011
Supported port number.
When SUS/RES(71pin)=“1”
0011 : 3 ports
When SUS/RES(71pin)=“0”
Combination with PSEL(66pin) input the supported number of port will be
selected. Please refer to 1.1 Cable Interface Pins.
0001 : 1 port
0010 : 2 port
0011 : 3 port
3R
010 Indicate the maximum speed that this node supports.
010: 98.304, 196.608 and 393.216 Mbps
4R
0010
Indicate worst case repeating delay time. 144+(2 x 20)=184 nsec
1 R/W 1 Link active.
1 : Enable
0 : Disable
The logical AND status of this bit and LPS pin.
State will be referred to “L bit” of Self-ID Packet#0.
1 R/W
See Contender.
Description “1” indicate this node support bus manager function. This bit will be referred
to “C bit” of Self-ID Packet#0.
The reset data is depending on CMC pin setting.
CMC pin condition
1: Pull up (Contender)
0: Pull down (Non Contender)
3R
010 The difference of repeating time (Max.-Min.). (2+1) x 20=60 nsec
Data Sheet S14452EJ1V0DS00
11
11 Page | ||
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