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UPD72107 の電気的特性と機能

UPD72107のメーカーはNECです、この部品の機能は「LAP-B CONTROLLER(Link Access Procedure Balanced mode)」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD72107
部品説明 LAP-B CONTROLLER(Link Access Procedure Balanced mode)
メーカ NEC
ロゴ NEC ロゴ 




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UPD72107 Datasheet, UPD72107 PDF,ピン配置, 機能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD72107
LAP-B CONTROLLER
Link Access Procedure Balanced mode
The µPD72107 is an LSI that supports LAP-B protocol specified by the ITU-T recommended X.25 on a single
chip.
FEATURES
• Complied with ITU-T recommended X.25 (LAP-B84
edition)
HDLC frame control
Sequence control
Flow control
• ITU-T recommended X.75 supported
• TTC standard JT-T90 supported
• Optional functions
Option frame
Global address frame
Error check deletion frame
• Powerful test functions
Data loopback function
Loopback test link function
Frame trace function
• Abundant statistical information
• Detailed mode setting function
• Modem control function
• On-chip DMAC (Direct Memory Access Controller)
24-bit address
Byte/word transfer enabled (switch with external pin)
• Memory-based interface
Memory-based command
Memory-based status
Memory-based transmit/receive data
• MAX.4 Mbps serial transfer rate
• NRZ, NRZI coding
ORDERING INFORMATION
Part Number
µPD72107CW
µPD72107GC-3B9
µPD72107L
Package
64-pin plastic shrink DIP (750 mils)
80-pin plastic QFP (14 x 14 mm)
68-pin plastic QFJ (950 x 950 mils)
The information in this document is subject to change without notice.
Document No. S12962EJ5V0DS00 (5th edition)
Date Published October 1998 N CP(K)
Printed in Japan
©
1998

1 Page





UPD72107 pdf, ピン配列
PIN CONFIGURATION (Top View)
64-pin plastic shrink DIP (750 mils)
µPD72107CW
IC
RxC
RxD
TxC
TxD
CTS
IC
RESET
NC
IC
B/W
PU
CLK
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16D8
A17D9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
µPD72107
64 RTS
63 CD
62 CRQ
61 AEN
60 ASTB
59 READY
58 HLDAK
57 HLDRQ
56 CLRINT
55 INT
54 UBE
53 MWR
52 MRD
51 GND
50 IOWR
49 IORD
48 CS
47 VCC
46 D7
45 D6
44 D5
43 D4
42 D3
41 D2
40 D1
39 D0
38 A23D15
37 A22D14
36 A21D13
35 A20D12
34 A19D11
33 A18D10
3


3Pages


UPD72107 電子部品, 半導体
µPD72107
1. PINS
1.1 Pin Functions
Pin Name
VCC
GND
CLK
(Clock)
RESET
(Reset)
PU
(Pull Up)
CS
(Chip Select)
MRD
(Memory Read)
MWR
(Memory Write)
IORD
(I/O Read)
IOWR
(I/O Write)
ASTB
(Address Strobe)
SDIP
Pin No.
47
14
51
13
QFP
Pin No.
68
70
27
28
74
26
QFJ
Pin No.
50
51
15
16
55
14
8 22 10
12 25 13
48 71 52
52 75 56
53 76 57
49 72 53
50 73 54
60 5 64
I/O
I
I
I
I
O
3-state
O
3-state
I
I
O
Active
Level
L
L
L
L
L
L
H
Function
+5 V power supply
Ground (0 V)
Note that there is more than one ground pin.
System clock input
Input clock of 1 MHz to 8.2 MHz.
Initializes the internal µPD72107. Active width of
more than 7 CLK clock cycles is required (clock
input is required).
After reset, this pin becomes a bus slave.
Pull up to high level when using in normal operation.
When bus master
Set to disable.
When bus slave
Read/write operation from the host processor at low
level is enabled.
When bus master
Reads the data of the external memory at low level.
When bus slave
High impedance
When bus master
Writes the data to the external memory at low level.
When bus slave
High impedance
This pin is used when the external host processor
reads the contents of the internal registers of the
µPD72107.
This pin is used when the external host processor
writes the data to the internal registers of the
µPD72107.
This pin is used to latch the address output from
the µPD72107 externally.
6

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
UPD7210

Intelligent Gpib Controller

NEC
NEC
UPD72103A

HDLC Controller

NEC
NEC
UPD72107

LAP-B CONTROLLER(Link Access Procedure Balanced mode)

NEC
NEC
uPD72107CW

LAP-B CONTROLLER(Link Access Procedure Balanced mode)

NEC
NEC


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