DataSheet.jp

UPD72042BGT の電気的特性と機能

UPD72042BGTのメーカーはNECです、この部品の機能は「LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD72042BGT
部品説明 LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL
メーカ NEC
ロゴ NEC ロゴ 




このページの下部にプレビューとUPD72042BGTダウンロード(pdfファイル)リンクがあります。

Total 30 pages

No Preview Available !

UPD72042BGT Datasheet, UPD72042BGT PDF,ピン配置, 機能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD72042A, 72042B
LSI DEVICES FOR Inter Equipment BusTM (IEBusTM)
PROTOCOL CONTROL
The µPD72042A and µPD72042B are microcomputer peripheral LSI devices for IEBus protocol control.
The µPD72042A and µPD72042B perform all the processing required for layers 1 and 2 of the IEBus. The devices
incorporate large transmission and reception buffers, allowing the microcomputer to perform IEBus operations without
interruption. They also contain an IEBus driver and receiver, allowing them to directly connected to the bus directly.
FEATURES
Control of layers 1 and 2 of the IEBus protocol
• Support of a multi-master scheme
• Broadcast function
• Two communication modes having different
transmission speeds can be selected.
Mode 0
Mode 1
When operating
at 6 MHz
Approx. 3.9 Kbps
Approx. 17 Kbps
When operating
at 6.29 MHz
Approx. 4.1 Kbps
Approx. 18 Kbps
q Built-in IEBus driver and receiver
q Transmission and reception buffers
Transmission buffer : 33 bytes, FIFO
Reception buffer
: 40 bytes, FIFO (capable of
holding more than one frame
of reception data.)
ORDERING INFORMATION
Microcomputer interface
Three-/two-wire serial I/O
• Transfer starting with MSB : µPD72042A
• Transfer starting with LSB : µPD72042B
Program crashes can be detected by means of a
watchdog timer.
Low power consumption (standby mode):
50 µA (max)
Oscillator frequency (fX): 6 MHz, 6.29 MHz
• frequency accuracy: ±1.5%
Operating voltage: 5 V ±10%
Part number
µPD72042AGT
µPD72042BGT
Package
16-pin plastic SOP (375 mil)
16-pin plastic SOP (375 mil)
Starting with MSB/LSB
MSB
LSB
The information in this document is subject to change without notice.
Document No. S13990EJ2V0DS00 (2nd edition)
(Previous No. ID-3649)
Date Published January 1999 N CP(N)
Printed in Japan
The mark shows major revised points.
©
1995

1 Page





UPD72042BGT pdf, ピン配列
BLOCK DIAGRAM
XI XO
µPD72042A, 72042B
Data link controller
Oscillation
control
section
Program
crash
detection
section
BUS +
BUS –
Internal bus
Receiver
Filter
Driver
Contention
detection
section
Parity generation
section
Parity detection
section
P/S conversion
section
Synchronization
control section
CTR
CMR
WDB
(5 bytes)
TBF
(33 bytes)
STR
FLG
RDB
(7 bytes)
CS
C/D
SCK
SI
(SIO)
SO
(NC)
SEL
Test circuit
Timing
generation
section
Frame data
control
section
RBF
(40 bytes)
IRQ
TEST
RESET
AVDD VDD GND
Remark The pin names in parentheses are used when two-wire serial I/O is selected.
DATA SHEET S13990EJ2V0DS00
3


3Pages


UPD72042BGT 電子部品, 半導体
µPD72042A, 72042B
1. PIN FUNCTIONS
1.1 PIN FUNCTIONS
Pin No. PinNote
I/ONote
1
SCK
Input
2 SI (SIO) Input (I/O)
3 SO (NC) Output
(none)
Function
I/O formatNote
Serial clock input pin for CPU interface
Serial data pin for CPU interface. (This pin
functions as an input pin when 3-wire serial
I/O mode is selected, or as an I/O pin when
2-wire serial I/O mode is selected.)
CMOS input
CMOS input
(CMOS I/O)
Serial data output pin for CPU interface. (The
pin functions as an output when 3-wire serial I/O
mode is selected. When 2-wire serial I/O mode
is selected, the pin is left open.)
CMOS output
(none)
When reset
[for both hardware
and software]
Input
Input
High-impedance
4 IRQ Output
5 C/D Input
6 XI
7 XO
8
GND
9
BUS–
I/O
10 BUS+
11 AVDD
12 SEL
Input
13 CS
Input
Output pin for making an interrupt request to the
CPU. When a return code or a program crash is
detected, a high-level signal is output on this pin
for at least 8 µs.
Input pin used to select control mode or data
read/write mode. When this pin is driven high,
internal register address setting and data read/
write are enabled. When the mode changes, the
serial clock counter is reset.
CMOS output
CMOS input
Pins for connecting a system clock resonator. A
6- or 6.29-MHz crystal or ceramic resonator
must be used. The accuracy of the frequency is
as follows;
Mode 0, 1: ±1.5%
Ground pin
I/O pins connected to the IEBus bus
Low level
Input
When reset by
hardware (Oscil-
lation stopped)
XI = GND
XO = High level
When reset by
software (Oscil-
lation continued)
High-impedance
Main power supply pin for the IEBus bus driver/
receiver. When used, this pin must be tied to
VDD.
Input pin used to select either 3- or 2-wire serial
I/O mode. A high-level signal on this pin selects
3-wire serial I/O mode. A low-level signal on this
pin selects 2-wire serial I/O mode.
CMOS input
Chip select pin. When this pin is driven low, the
serial interface is enabled. When this pin is
driven high, the SO pin becomes high-imped-
ance, and the serial clock counter is reset.
CMOS input
Input
Input
Note Parentheses indicate the state corresponding to two-wire serial I/O mode.
6 DATA SHEET S13990EJ2V0DS00

6 Page



ページ 合計 : 30 ページ
 
PDF
ダウンロード
[ UPD72042BGT データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
UPD72042BGT

LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL

NEC
NEC


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap