|
|
PDF UPD720130 Data sheet ( Hoja de datos )
| Número de pieza | UPD720130 | |
| Descripción | USB2.0 to IDE Bridge | |
| Fabricantes | NEC | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de UPD720130 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD720130
USB2.0 to IDE Bridge
The µPD720130 is designed to perform a bridge between USB 2.0 and ATA/ATAPI. The µPD720130 complies
with the Universal Serial Bus Specification Revision 2.0 full-/high-speed signaling and works up to 480 Mbps. The
µPD720130 is integrated CISC processor, ATA/ATAPI controller, endpoint controller (EPC), serial interface engine
(SIE), and USB2.0 transceiver into a single chip. The USB2.0 protocol and class specific protocol (bulk only
protocol) are handled by USB2.0 transceiver, SIE, and EPC. And the transport layer is performed by V30MZ CISC
processor which is in the µPD720130. The software to control the µPD720130 is located in an embedded ROM. In
the future, the µPD720130 will be released to support external Flash Memory / EEPROM™ option to update function
by firmware.
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.
µPD720130 User’s Manual: S16412E
FEATURES
• Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 12/480 Mbps)
• Compliant with ATA/ATAPI-6 (LBA48, PIO Mode 0-4, Multi Word DMA Mode 0-2, Ultra DMA Mode 0-4)
• USB2.0 high-speed bus powered device capability
• Certified by USB implementers forum and granted with USB 2.0 high-speed Logo (TID :40320125)
• One USB2.0 high-speed transceiver / receiver with full-speed transceiver / receiver
• USB2.0 High-speed or Full-speed packet protocol sequencer (Serial Interface Engine)
• Automatic chirp assertion and full-/high-speed mode change
• USB Reset, Suspend and Resume signaling detection
• Supports power control functionality for IDE device as CD-ROM and HDD
• Supports set feature (TEST_MODE) functionality
• System Clock is generated by 30 MHz X’tal
• 2.5 V and 3.3 V power supply
ORDERING INFORMATION
Part Number
µPD720130GC-9EU
µPD720130GC-9EU-SIN
Package
100-pin plastic TQFP (fine pitch) (14 × 14)
100-pin plastic TQFP (fine pitch) (14 × 14)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S16302EJ3V0DS00 (3rd edition)
Date Published June 2003 NS CP (K)
Printed in Japan
The mark shows major revised points.
2002
1 page  
µPD720130
1. PIN INFORMATION
Pin Name
I/O
Buffer Type
Active
Level
Function
(1/2)
XIN I 2.5 V Input
System clock input or oscillator In
XOUT
O 2.5 V Output
Oscillator out
RESETB
I 3.3 V Schmitt Input
Low Asynchronous reset signaling
MD(1:0)
I 3.3 V Input
Function mode setting
IDECS(1:0)B
O (I/O) 5 V tolerant Output
Low IDE host chip select
IDEA(2:0)
O (I/O) 5 V tolerant Output
IDE address bus
IDEINT
I (I/O) 5 V tolerant Input
High
IDE interrupt request from device to host
IDEDAKB
O (I/O) 5 V tolerant Output
Low IDE DMA acknowledge
IDEIORDY
I (I/O) 5 V tolerant Input
High
IDE IO channel ready
IDEIORB
O (I/O) 5 V tolerant Output
Low IDE IO read strobe
IDEIOWB
O (I/O) 5 V tolerant Output
Low IDE IO write strobe
IDEDRQ
I (I/O) 5 V tolerant Input
High
IDE DMA request from device to host
IDED(15:0)
I/O 5 V tolerant I/O
IDE data bus
IDERSTB
O (I/O) 5 V tolerant Output
Low IDE reset from host to device
DCC
I (I/O) 3.3 V Input
IDE controller operational mode setting
DV(1:0)
I (I/O) 3.3 V Input
Device select
CLC
I (I/O) 3.3 V Input
System clock setting
PWR
I (I/O) 3.3 V Input
Bus powered /self-powered select
CMB_BSY
O (I/O) 3.3 V Output
Combo IDE bus busy
CMB_STATE
I (I/O) 3.3 V Input
Combo IDE bus state
DPC
O (I/O) 3.3 V Output
Power control signaling for IDE device
SDA
I/O 3.3 V I/O
Serial ROM data signaling
SCL
VBUS
I/O 3.3 V I/O
I 5 V Schmitt Input Note
Serial ROM clock signaling
VBUS monitoring
DP I/O USB high speed D+ I/O
DM I/O USB high speed D− I/O
USB’s high speed D+ signal
USB’s high speed D− signal
RSDP
RSDM
RPU
O USB full speed D+ Output
O USB full speed D− Output
A USB Pull-up control
USB’s full speed D+ signal
USB’s full speed D− signal
USB’s 1.5 kΩ pull-up resistor control
RREF
A Analog
Reference resistor
SPD
I (I/O) 3.3 V Input
NEC private
SMC
I 3.3 V Input
Scan mode control
TEST(3:0)
I 3.3 V Input
Test mode setting
Note
VBUS pin may be used to monitor for VBUS line even if VDD33, VDD25, and AVDD25 are shut off. System must
ensure that the input voltage level for VBUS pin is less than 3.0 V due to the absolute maximum rating is
not exceeded.
Data Sheet S16302EJ3V0DS
5
5 Page 
µPD720130
2.4 Combo Mode Function
The µPD720130 can be used to realize that two IDE controller chips control one target IDE device in one
system. To realize IDE bus arbitration between two IDE controller chips, the µPD720130 has CMB_BSY and
CMB_STATE. Combo mode is enabled when PWR = 0 and CLC = 1.
CMB_BSY and CMB_STATE connect to other IDE controller chip as follows.
Figure 2-1. CMB_BSY and CMB_STATE Connection between Two IDE Controller Chips
µ PD720130
Other IDE controller
CMB_STATE
CMB_BSY
IDE Bus Grant
IDE Bus Request
Pin Name
CMB_STATE
CMB_BSY
Table 2-5. Description of CMB_BSY and CMB_STATE
Direction
IN
OUT
Value
0
1
0
1
Description
Other IDE controller does not require or does not use IDE bus.
Other IDE controller requires or is using IDE bus.
The µPD720130 does not require or does not use IDE bus.
The µPD720130 requires or is using IDE bus.
Data Sheet S16302EJ3V0DS
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UPD720130.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| UPD720130 | USB2.0 to IDE Bridge | NEC |
| UPD720133 | MOS Integrated Circuit | NEC |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |