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PDF UPD70F3040 Data sheet ( Hoja de datos )
| Número de pieza | UPD70F3040 | |
| Descripción | V850/SV1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS | |
| Fabricantes | NEC | |
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PREPLRIEMLINIMADIRNAYATRAPYRSODHDAEUETATCTSHINEFEOTRMATION
MOS INTEGRATED CIRCUIT
µPD70F3040, 70F3040Y
V850/SV1TM
32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD70F3040 and µPD70F3040Y are products that substitute flash memory for the mask ROM of the
µPD703039, 703040, 703041 and µPD703039Y, 703040Y, 703041Y, respectively. Since the µPD70F3040 and
70F3040Y can be read and written while mounted on the board, these products are ideal for evaluation during
system development, multiple-version small-scale production or quick product release.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850/SV1 User’s Manual Hardware:
U14462E
V850 FamilyTM User’s Manual Architecture: U10243E
FEATURES
• Pin compatible with µPD703039, 703040, 703041, 703039Y, 703040Y, and 703041Y
• For mass production, these can be replaced by a mask ROM version.
µPD70F3040 → µPD703039, 703040, 703041
µPD70F3040Y → µPD703039Y, 703040Y, 703041Y
ORDERING INFORMATION
Part Number
µPD70F3040GM-UEU
µPD70F3040YGM-UEU
Package
176-pin plastic LQFP (fine-pitch) (24 × 24 mm)
176-pin plastic LQFP (fine-pitch) (24 × 24 mm)
DIFFERENCES BETWEEN V850/SV1 PRODUCTS
µPD70F3040
µPD70F3040Y
µPD703039
µPD703039Y
µPD703040
µPD703040Y
µPD703041
µPD703041Y
Internal ROM
256 KB (flash memory)
256 KB (mask ROM)
192 KB (mask ROM)
Internal RAM
16 KB
8 KB
16 KB
8 KB
I2C
None
Provided
None
Provided
None
Provided
None
Provided
VPP Pin
Provided
None
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14622EJ1V0DS00 (1st edition)
Date Published March 2000 N CP(K)
Printed in Japan
©
2000
1 page  
µPD70F3040, 70F3040Y
CONTENTS
1. PIN FUNCTIONS.................................................................................................................................. 6
1.1 Port Pins.................................................................................................................................................... 6
1.2 Non-Port Pins........................................................................................................................................... 10
1.3 Pin I/O Circuits, I/O Buffer Supply, and Recommended Connection of Unused Pins ....................... 14
2. ELECTRICAL SPECIFICATIONS...................................................................................................... 18
3. PACKAGE DRAWING ....................................................................................................................... 39
4. RECOMMENDED SOLDERING CONDITION.................................................................................. 40
Preliminary Data Sheet U14622EJ1V0DS00
5
5 Page 
µPD70F3040, 70F3040Y
Pin Name
I/O
INTTCLR8
Input
INTTI8
Input
INTTI9
KR0 to KR7
Input
LBEN
Output
NMI Input
PWM0 to PWM3 Output
RD Output
RESET
Input
RTP00 to RTP07 Output
RTP10 to RTP17
RTPTRG0
Input
RTPTRG1
R/W Output
RXD0
Input
RXD1
SCK0
I/O
SCK1
SCK2
SCK3
SCK4
SCL0
I/O
SCL1
SDA0
I/O
SDA1
SI0 Input
SI1
SI2
SI3
SI4
SO0
Output
SO1
SO2
SO3
SO4
TCLR8
Input
PULL
No
No
Yes
No
Yes
No
No
–
Yes
Yes
No
No
Yes
Yes
No
Yes
Yes
Yes
No
Yes
No
No
Function
External interrupt request input (digital noise elimination)
Key return input
Lower byte enable signal output for external data bus
Non-maskable interrupt request input
Output of PWM channels 0 to 3
Bus read strobe signal output
System reset input
Real-time output port
RTP external trigger input
External read/write status output
Serial receive data input for UART0 and UART1
Serial clock I/O for CSI0 to CSI3 (3-wire mode)
Variable-length CSI4 serial clock I/O
Serial clock I/O for I2C0 and I2C1
(µPD70F3040Y)
Serial transmit/receive data I/O for I2C0 and I2C1
(µPD70F3040Y)
Serial receive data input for CSI0 to CSI3 (3-wire mode)
Variable-length CSI4 serial receive data input (3-wire mode)
Serial transmit data output for CSI0 to CSI3
Variable-length CSI4 serial transmit data output
External clear input for TM8
Remark PULL: On-chip pull-up resistor
(2/4)
Alternate Function
P135/TCLR8
P134/TI8
P144/TI9
P170 to P177
P90/WRL
P00
P160 to P163
P93/DSTB
–
P100 to P107
P150 to P157
P06
P146
P92/WRH
P13/SI1
P23/SI3
P12/SCL0
P15/ASCK0
P22/SCL1
P25/ASCK1
P122
P12/SCK0
P22/SCK2
P10/SI0
P20/SI2
P10/SDA0
P13/RXD0
P20/SDA1
P23/RXD1
P120
P11
P14/TXD0
P21
P24/TXD1
P121
P135/INTTCLR8
Preliminary Data Sheet U14622EJ1V0DS00
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UPD70F3040.PDF ] | |
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