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PDF UPD705102GM-133-8ED Data sheet ( Hoja de datos )
| Número de pieza | UPD705102GM-133-8ED | |
| Descripción | V832TM 32-BIT MICROPROCESSOR | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD705102
V832TM
32-BIT MICROPROCESSOR
DESCRIPTION
The µPD705102 (V832) is a 32-bit RISC microprocessor for embedded control applications, with a high-
performance 32-bit V830TM processor core and many peripheral functions such as a SDRAM/ROM controller, 4-
channel DMA controller, real-time pulse unit, serial interface, interrupt controller, and power management.
In addition to high interrupt response speed and optimized pipeline structure, the V832 offers sum-of-products
operation instructions, concatenated shift instructions, and high-speed branch instructions to realize multimedia
functions, and therefore can provide high performance in multimedia systems such as Internet/intra-net systems, car
navigation systems, digital still cameras, and color faxes.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V832 User’s Manual — Hardware:
U13577E
V830 FamilyTM User’s Manual — Architecture: U12496E
FEATURES
• CPU function
• V830-compatible instructions
• Instruction cache:
4 Kbytes
• Instruction RAM:
4 Kbytes
• Data cache:
4 Kbytes
• Data RAM:
4 Kbytes
• Minimum number of instruction
execution cycles:
1 cycle
• Number of general purpose
registers:
32 bits × 32
• Memory space and I/O space: 4 Gbytes each
• Interrupt/exception processing function
• Non-maskable: External input: 1
• Maskable:
External input: 8 (of which 4 are
multiplexed with
internal sources)
Internal source: 11 types
• Bus control function
• Wait control function
• Memory access control function
• DMA controller: 4 channels
• Serial interface function
• Asynchronous serial interface (UART): 1 channel
• Clocked serial interface (CSI):
1 channel
• Dedicated baud rate generator (BRG): 1 channel
• Timer/counter function
• 16-bit timer/event counter: 1 channel
• 16-bit interval timer:
1 channel
• Port function: 21 I/O ports
• Clock generation function: PLL clock synthesizer (6× or
8× multiplication)
• Standby function: HALT, STOP, and power manage-
ment modes
• Debug function
• Debug-dedicated synchronous serial
interface:
1 channel
• Trace-dedicated interface:
1 channel
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. U13675EJ2V1DS00 (2nd edition)
Date Published July 1999 N CP(K)
Printed in Japan
The mark shows major revised points.
©
1999
1 page  
µPD705102
CONTENTS
1. PIN FUNCTIONS .................................................................................................................................. 6
1.1 Port Pins ....................................................................................................................................................... 6
1.2 Non-Port Pins ............................................................................................................................................... 7
2. INTERNAL UNITS ................................................................................................................................ 9
3. CPU FUNCTION ................................................................................................................................. 11
4. INTERRUPT/EXCEPTION PROCESSING FUNCTION ..................................................................... 12
5. BUS CONTROL FUNCTION .............................................................................................................. 14
6. WAIT CONTROL FUNCTION ............................................................................................................. 14
7. MEMORY ACCESS CONTROL FUNCTION ...................................................................................... 15
7.1 SDRAM Control Function .......................................................................................................................... 15
7.2 Page-ROM Control Function ..................................................................................................................... 17
8. DMA FUNCTION ................................................................................................................................ 18
9. SERIAL INTERFACE FUNCTION ...................................................................................................... 20
9.1 Asynchronous Serial Interface (UART) .................................................................................................... 20
9.2 Clocked Serial Interface (CSI) ................................................................................................................... 22
9.3 Baud Rate Generator (BRG) ...................................................................................................................... 23
10. TIMER/COUNTER FUNCTION .......................................................................................................... 24
11. PORT FUNCTION .............................................................................................................................. 27
12. CLOCK GENERATION FUNCTION ................................................................................................... 32
13. STANDBY FUNCTION ....................................................................................................................... 33
14. RESET/NMI CONTROL FUNCTION .................................................................................................. 35
15. INSTRUCTIONS ................................................................................................................................. 36
15.1 Instruction Format ..................................................................................................................................... 36
15.2 Instructions (Listed Alphabetically) ......................................................................................................... 38
16. ELECTRICAL SPECIFICATIONS ...................................................................................................... 48
17. PACKAGE DRAWING ........................................................................................................................ 75
18. RECOMMENDED SOLDERING CONDITIONS ................................................................................. 76
Data Sheet U13675EJ2V1DS00
5
5 Page 
3. CPU FUNCTION
The features of the CPU function are as follows:
• High-performance 32-bit architecture for embedded control applications
• Cache memory
Instruction cache: 4 Kbytes
Data cache:
4 Kbytes
• Internal RAM
Instruction RAM: 4 Kbytes
Data RAM:
4 Kbytes
• 1-clock pitch pipeline structure
• 16-/32-bit length instruction format
• Address/data separated type bus
• 4-Gbyte linear address
• Thirty-two 32-bit general registers
• Register/flag hazard interlock is handled by hardware
• 16 levels of interrupt response
• 16-bit bus fixed function
• 16-bit bus system can be constructed
• Ideal instructions for any application field:
• Sum-of-products operation
• Saturation operation
• Branch prediction
• Concatenation shift
• Block transfer instruction
µPD705102
Data Sheet U13675EJ2V1DS00
11
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