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VP2615CGGH1R の電気的特性と機能

VP2615CGGH1RのメーカーはMitel Networks Corporationです、この部品の機能は「H.261 Decoder」です。


製品の詳細 ( Datasheet PDF )

部品番号 VP2615CGGH1R
部品説明 H.261 Decoder
メーカ Mitel Networks Corporation
ロゴ Mitel Networks Corporation ロゴ 




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VP2615CGGH1R Datasheet, VP2615CGGH1R PDF,ピン配置, 機能
Supersedes January 1996 edition, DS3479 - 3.0
VP2VP6216155
H.261 Decoder
DS3479 - 4.0 June 1996
FEATURES
s Inputs run length coded transform data
s Outputs 8 bit pixels in YUV block format
s Up to full CIF resolution and 30 Hz frame rates
s Supports motion compensation with up to 15 pixel
movement
s On chip frame store controller
s 100 pin QFP package
ASSOCIATED PRODUCTS
s VP510 Colour Space Converter
s VP520S Three Channel Video Filter
s VP2611 Integrated H261 Encoder
s VP2612 Video Multiplexer
s VP2614 Video Demultiplexer
DESCRIPTION
The VP2615 decoder forms part of a chip set for use in
video conferencing and video telephony applications. It
conforms to the CCITT H261 standard, and will decode data
coded with full or quarter CIF resolution at frame rates up to 30
Hz.
It accepts run length coded coefficients which have already
been error corrected and Huffman decoded, and produces
multiplexed YUV data in macro block format after a pipeline
delay of two MacroBlocks. As shown in Figure 1, other devices
in the chip set then convert this data into full resolution,
component or composite, video.
The incoming run length coded data is converted to
individual coefficient values in the correct order. Data
reconstruction is then performed on a block by block basis by
multiplying the quantized coefficients with the original
quantization value, and then applying the inverse cosine
transform. In the inter frame mode this data is then added to
the motion compensated block from the previous frame. This
block can be passed through a low pass filter when required.
A frame store controller produces addresses which allow the
best fit block to be read from the frame store, and which also
allow the store to be updated with reconstructed data. Refresh
cycles are generated when necessary.
SYSTEM
CONTROLLER
USER
INTERFACE
H261
BIT
STREAM
VP2614
VIDEO DEMUX
RECEIVE
BUFFER
32K X 8
RLC
DATA
ADR
VP2615
VIDEO
DECODER
CIF FRAME
STORE
128K X 16
FRMOUT
VP520
3 CHANNEL
VIDEO FILTER
Y/CR/CB
MACRO
BLOCK
DATA
ADR
DATA
TWO CIF
FRAME STORES
256K X 16
VP530
NTSC/PAL
ENCODER
VP510
COLOUR SPACE
CONVERTER
COMP
NTSC/PAL
RGB
OUTPUTS
Fig 1 : Typical Video Conferencing Receiver
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VP2615CGGH1R pdf, ピン配列
VP2615
OPERATION OF MAJOR BLOCKS
Run Length Decode
This block converts the run length coded data into 64
individual coefficient values, inserting zero value coefficients
where required. It then re-orders these 8 bit quantized DCT
coefficients from the zig zag arrangement into normal 8 x 8
format.
Inverse Quantise
This circuit reconstructs the 12 bit DCT coefficients from
the 8 bit quantized coefficients using the 5 bit Quantization
Value. This is performed using the following formulae.
If QUANT is odd :
REC = QUANT*(2*LEVEL+1) : LEVEL > 0
REC = QUANT*(2*LEVEL-1) : LEVEL < 0
If QUANT is even :
REC = QUANT*(2*LEVEL+1)-1 : LEVEL > 0
REC = QUANT*(2*LEVEL-1)+1 : LEVEL < 0
For Intra coded DC coefficients :
REC = 8*LEVEL
except if LEVEL=255 when REC=1024
If LEVEL=0 then REC=0 in all cases.
The reconstructed values (REC) are passed through a
clipping circuit in case of arithmetic overflow.
Inverse DCT
This circuit performs an Inverse Discrete Cosine Trans-
form on an 8x8 block of 12 bit coefficients outputting 9 bit
signed pixel data. This IDCT fully meets the CCITT specifica-
tion.
Frame Store Interface
The whole of the previous picture is stored in either two
external 64K x 16 DRAMs, or in a single 256 k x 16 DRAM, or
in four 256K x 4 DRAM's. A bit in the user defined Input Set Up
Data determines whether 64K or 256K DRAM's are to be
used. In the latter case, use OE1 as ADR8, RW1 as R/W and
do not connect RW2 and OE2.Table 1 specifies the worst case
maximum and minimum times which must be achieved by the
DRAM for correct operation with the VP2615. Times in the
DRAM specification must be less than or equal to the times
stated.
The Frame Store Interface manages all read and write
operations to these DRAM's. During the course of each
MacroBlock, the "Best Fit" MacroBlock is read from the
DRAMs and the fully processed MacroBlock is written back. In
this way, the previous frame is continually updated. The
DRAM controller also takes care of refresh for the DRAMs.
Figure 3 illustrates the effects of the pipeline delays
through the device; whilst macro block 3 is being input the
previous macroblock (2) is being decoded and needs the
equivalent macroblock from the previous frame to be read
from the frame store. At the same time macroblock 1, which
has already been decoded, is being written to the frame store
DIN Input
Frame Store Read
Frame Store Write
YUV Output
Minimum of
2048 cycles
MB3
MB4
MB5
MB2
MB3
MB4
MB1
MB2
MB3
MB1
MB2
MB3
MB6
MB5
MB4
MB4
Fig 3 : MacroBlock Pipelining
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
t RAC
t CAC
t RP
t CP
t RAS
t CAS
t REF
Access time from RAS
Access time from CAS
RAS precharge time
CAS precharge time
RAS pulse width
CAS pulse width
Time to refresh 256 rows
-
-
50ns or under
15ns or under
90ns or under
50ns or under
-
105ns or under
25ns or under
-
-
-
-
0.25ms or over
N.B. All times are quoted assuming 27MHz operation. For lower clock
frequencies increase the above values proportionately.
Table 1. External DRAM Timing Requirements
3


3Pages


VP2615CGGH1R 電子部品, 半導体
VP2615
WRITING DATA ONTO THE CBUS:
WRITING DATA FROM THE CBUS:
This diagram shows a typical instruction and associated data field being written to the device.
CEN
10ns
20ns
10ns
CADR
CSTR
CBUS
I/P
20ns
20ns
10ns
20ns
20ns
10ns
INSTRUCTION
20ns
20ns
10ns
20ns
20ns
10ns
DATA IN
READING INFORMATION ON CBUS :
This diagram shows a typical instruction and associated data field being read from the device.
CEN
CADR
CSTR
CBUS
20ns
20ns
10ns
10ns
Th
20ns
20ns
10ns
INSTRUCTION
20ns
50ns
10ns
10ns
20ns
20ns
20ns*
20ns*
10ns
20ns*
DATA OUT
If Th is less than 5 ns then CBUS may be driven by the VP2615until CEN going high eventually turns off
the drivers. It will not prevent correct data being read when CEN again goes active
N.B. All timings shown are minimum values except those marked * which are maximums.
Fig 7 : CBUS Timing
coded picture. As explained in the previous section, however,
it requires to be supplied with two macroblocks from the next
picture before a complete frame is fully decoded. The stand-
ard macroblock internal configuration is shown in Figure 5.
Output timing is shown in Figure 6. VPIX is toggled high
each time a valid pixel is available at the output pins, and
remains low when no pixel data is output. MBOUT is used to
define the boundaries between MacroBlocks, but is not used
when the device is directly connected to the VP520. The
Frame Ready Output nominally goes high on the same SYSCLK
edge as the first MBOUT goes high, and returns low when the
last MBOUT goes low. This will actually be after two macrob-
locks from the next frame have been supplied as inputs, but
this gap will not effect the operation of the VP520 which
converts macro block data to full resolution line data. The first
VPIX strobe produced after MBOUT goes high, will go high
after two SYSCLK periods, with the data being valid for two
SYSCLK periods either side of this edge. These delays are
subject to internal differential delays and will not be precise
clock period delays.
CBUS Control Port
The CBUS control port is used to input control and setup
information and also to output status information. In order to
save on pin count, a microprocessor driving this port is
required to execute two I/O instructions in order to transfer a
single byte of information to or from the device. The first
transfer is always a write operation, with a low level on the
single address line which is used by the interface. Data on the
bus then defines the instructions listed in Table 3. The second
transfer can be a read or write operation as necessary, but the
address line must then be high with the set up time given in
Figure 7.
In addition to the single addresss line (CADR), data
transfers use a control strobe (CSTR) which is only effective
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部品番号部品説明メーカ
VP2615CGGH1R

H.261 Decoder

Mitel Networks Corporation
Mitel Networks Corporation


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