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VIPer50SP の電気的特性と機能

VIPer50SPのメーカーはSTMicroelectronicsです、この部品の機能は「SMPS PRIMARY I.C.」です。


製品の詳細 ( Datasheet PDF )

部品番号 VIPer50SP
部品説明 SMPS PRIMARY I.C.
メーカ STMicroelectronics
ロゴ STMicroelectronics ロゴ 




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VIPer50SP Datasheet, VIPer50SP PDF,ピン配置, 機能
VIPer50/SP
® - VIPer50A/ASP
SMPS PRIMARY I.C.
TYPE
VIPer50/SP
VIPer50A/ASP
VDSS
620V
700V
In
1.5 A
1.5 A
RDS(on)
5
5.7
s ADJUSTABLE SWITCHING FREQUENCY UP
TO 200 kHz
s CURRENT MODE CONTROL
s SOFT START AND SHUT DOWN CONTROL
s AUTOMATIC BURST MODE OPERATION IN
STAND-BY CONDITION ABLE TO MEET
“BLUE ANGEL” NORM (<1W TOTAL POWER
CONSUMPTION)
s INTERNALLY TRIMMED ZENER REFERENCE
s UNDERVOLTAGE LOCK-OUT WITH
HYSTERESIS
s INTEGRATED START-UP SUPPLY
s AVALANCHE RUGGED
s OVERTEMPERATURE PROTECTION
s LOW STAND-BY CURRENT
s ADJUSTABLE CURRENT LIMITATION
BLOCK DIAGRAM
10
PENTAWATT HV
1
PowerSO-10
PENTAWATT HV
(022Y)
DESCRIPTION
VIPer50/50A, made using VIPower M0
Technology, combines on the same silicon chip a
state-of-the-art PWM circuit together with an
optimized high voltage avalanche rugged Vertical
Power MOSFET (620V or 700V / 1.5A).
Typical applications cover off line power supplies
with a secondary power capability of 25W in wide
range condition and 50W in single range or with
doubler configuration. It is compatible from both
primary or secondary regulation loop despite
using around 50% less components when
compared with a discrete solution. Burst mode
operation is an additional feature of this device,
offering the possibility to operate in stand-by
mode without extra components.
OSC
DRAIN
ON/OFF
OSCILLATOR
SECURITY PWM
LATCH
LATCH
VDD
UVLO
LOGIC
R/S FF Q
S
S
R1 FF Q
R2 R3
OVERTEMP.
DETECTOR
0.5 V +
_
ERROR
_ AMPLIFIER
13 V +
4.5 V
1.7 µ s
DELAY
250 ns
BLANKING
0.5V
++ _
_
2 V/A
CURRENT
AMPLIFIER
April 2002
COMP
SOURCE
1/23
1

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VIPer50SP pdf, ピン配列
VIPer50/SP - VIPer50A/ASP
ORDERING NUMBERS
PENTAWATT HV
VIPer50
VIPer50A
PENTAWATT HV (022Y)
VIPer50 (022Y)
VIPer50A (022Y)
PINS FUNCTIONAL DESCRIPTION
PowerSO-10
VIPer50SP
VIPer50ASP
DRAIN PIN:
Integrated Power MOSFET drain pin. It provides
internal bias current during start-up via an
integrated high voltage current source which is
switched off during normal operation. The device
is able to handle an unclamped current during its
normal operation, assuring self protection against
voltage surges, PCB stray inductance, and
allowing a snubberless operation for low output
power.
SOURCE Pin:
Power MOSFET source pin. Primary side circuit
common ground connection.
VDD Pin:
This pin provides two functions:
- It corresponds to the low voltage supply of the
control part of the circuit. If VDD goes below 8V,
the start-up current source is activated and the
output power MOSFET is switched off until the
VDD voltage reaches 11V. During this phase,
the internal current consumption is reduced,
the VDD pin sources a current of about 2mA
and the COMP pin is shorted to ground. After
that, the current source is shut down, and the
device tries to start up by switching again.
- This pin is also connected to the error amplifier,
in order to allow primary as well as secondary
regulation configurations. In case of primary
regulation, an internal 13V trimmed reference
voltage is used to maintain VDD at 13V. For
secondary regulation, a voltage between 8.5V
and 12.5V will be put on VDD pin by transformer
design, in order to stick the output of the
transconductance amplifier to the high state.
The COMP pin behaves as a constant current
source, and can easily be connected to the
output of an optocoupler. Note that any
overvoltage due to regulation loop failure is still
detected by the error amplifier through the VDD
voltage, which cannot overpass 13V. The
output voltage will be somewhat higher than the
nominal one, but still under control.
COMP PIN:
This pin provides two functions:
- It is the output of the error transconductance
amplifier, and allows for the connection of a
compensation network to provide the desired
transfer function of the regulation loop. Its
bandwidth can easily be adjusted to the
needed value with usual components value. As
stated above, secondary regulation
configurations are also implemented through
the COMP pin.
- When the COMP voltage goes below 0.5V, the
shut-down of the circuit occurs, with a zero
duty cycle for the power MOSFET. This feature
can be used to switch off the converter, and is
automatically activated by the regulation loop
(whatever is the configuration) to provide a
burst mode operation in case of negligible
output power or open load condition.
OSC PIN:
An Rt-Ct network must be connected on that pin to
define the switching frequency. Note that despite
the connection of Rt to VDD, no significant
frequency change occurs for VDD varying from 8V
to 15V. It also provides a synchronization
capability, when connected to an external
frequency source.
3/23
1


3Pages


VIPer50SP 電子部品, 半導体
Figure 1: VDD Regulation Point
ICOMP
ICOMPHI
0
Slope =
Gm in mA/V
VDD
ICOMPLO
VDDreg
FC00150
Figure 3: Transition Time
ID
VDS
10%Ipeak
90%VD
t
10% VD
tf
t
tr
FC00160
Figure 5: Breakdown Voltage Vs. Temperature
1.15
BVDSS
(Normalized)
1.1
F C00180
1.05
1
0.95
0
20 40 60 80 100 120
Temperature (°C)
VIPer50/SP - VIPer50A/ASP
Figure 2: Undervoltage Lockout
ID D
ID D0
IDDch
VDD h y st
VDD o ff
VDS= 3 5 V
Fsw = 0
VVDDon DD
FC00170
Figure 4: Shut Down Action
VOSC
VCOMP
VCOMPth
ID
tDISsu
t
t
t
ENABLE
ENABLE
DISABLE
FC00060
Figure 6: Typical Frequency Variation
1
(%)
0
FC00190
-1
-2
-3
-4
-5
0 20 40 60 80 100 120 140
Temperature (°C)
6/23

6 Page



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共有リンク

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部品番号部品説明メーカ
VIPer50SP

SMPS PRIMARY I.C.

STMicroelectronics
STMicroelectronics


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