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X25138S8I-V の電気的特性と機能

X25138S8I-VのメーカーはXicorです、この部品の機能は「5MHz SPI Serial E2PROM with Block Lock PROTECTION」です。


製品の詳細 ( Datasheet PDF )

部品番号 X25138S8I-V
部品説明 5MHz SPI Serial E2PROM with Block Lock PROTECTION
メーカ Xicor
ロゴ Xicor ロゴ 




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X25138S8I-V Datasheet, X25138S8I-V PDF,ピン配置, 機能
128K
X25138
16K x 8 Bit
5MHz SPI Serial E2PROM with Block LockTM Protection
FEATURES
5MHz Clock Rate
Low Power CMOS
<1mA Standby Current
<5mA Active Current
2.5V To 5.5V Power Supply
SPI Modes (0,0 & 1,1)
16K X 8 Bits
32 Byte Page Mode
Block Lock™ Protection
Protect 1/4, 1/2 or all of E2PROM Array
Programmable Hardware Write Protection
In-Circuit Programmable ROM Mode
Built-in Inadvertent Write Protection
Power-Up/Down protection circuitry
Write Enable Latch
Write Protect Pin
Self-Timed Write Cycle
5ms Write Cycle Time (Typical)
High Reliability
Endurance: 100,000 cycles
Data Retention: 100 Years
ESD protection: 2000V on all pins
Packages
8-Lead XBGA
8, 14-Lead SOIC
8-Lead PDIP
8-Lead TSSOP
FUNCTIONAL DIAGRAM
STATUS
REGISTER
WRITE
PROTECT
LOGIC
SO
SI
SCK
CS
HOLD
COMMAND
DECODE
AND
CONTROL
LOGIC
DESCRIPTION
The X25138 is a CMOS 128K-bit serial E2PROM,
internally organized as 16K x 8. The X25138 features
a Serial Peripheral Interface (SPI) and software
protocol allowing operation on a simple three-wire bus.
The bus signals are a clock input (SCK) plus separate
data in (SI) and data out (SO) lines. Access to the
device is controlled through a chip select (CS) input,
allowing any number of devices to share the same
bus.
The X25138 also features two additional inputs that
provide the end user with added flexibility. By
asserting the HOLD input, the X25138 will ignore tran-
sitions on its inputs, thus allowing the host to service
higher priority interrupts. The WP input can be used as
a hardwire input to the X25138 disabling all write
attempts to the status register, thus providing a mech-
anism for limiting end user capability of altering 0, 1/4,
1/2 or all of the memory.
The X25138 utilizes Xicor’s proprietary Direct WriteTM
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
X DECODE
LOGIC
128
16K BYTE
ARRAY
128 X 256
128
128 X 256
256
256 X 256
WRITE
CONTROL
AND
WP
TIMING
LOGIC
Direct WriteÔ and Block LockÔ Protection is a trademark of Xicor, Inc.
ÓXicor, Inc. 1998 Patents Pending
7056–1.5 8/13/98 T2/C0/D1 EW
1
32 8
Y DECODE
DATA REGISTER
7037 FRM F01
Characteristics subject to change without notice

1 Page





X25138S8I-V pdf, ピン配列
X25138
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
PRINCIPLES OF OPERATION
The X25138 is a 16K x 8 E2PROM designed to inter-
face directly with the synchronous serial peripheral
interface (SPI) of many popular microcontroller fami-
lies.
The X25138 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising SCK. CS must be LOW and the HOLD and
WP inputs must be HIGH during the entire operation.
Table 1 contains a list of the instructions and their
opcodes. All instructions, addresses and data are
transferred MSB first.
Data input is sampled on the first rising edge of SCK
after CS goes LOW. SCK is static, allowing the user to
stop the clock and then resume operations. If the clock
line is shared with other peripheral devices on the SPI
bus, the user can assert the HOLD input to place the
X25138 into a “PAUSE” condition. After releasing
HOLD, the X25138 will resume operation from the
point when HOLD was first asserted.
Write Enable Latch
The X25138 contains a “write enable” latch. This latch
must be SET before a write operation will be
completed internally. The WREN instruction will set the
latch and the WRDI instruction will reset the latch. This
latch is automatically reset upon a power-up condition
and after the completion of a byte, page, or status
register write cycle.
Status Register
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is
formatted as follows:
7 654 3 2 1 0
WPEN X X X BL1 BL0 WEL WIP
7037 FRM T02
WPEN, BL0 and BL1 are set by the WRSR instruction.
WEL and WIP are read-only and automatically set by
other operations.
The Write-In-Process (WIP) bit indicates whether the
X25138 is busy with a write operation. When set to a
“1”, a write is in progress, when set to a “0”, no write is
in progress. During a write, all other bits are set to “1”.
The Write Enable Latch (WEL) bit indicates the status
of the “write enable” latch. When set to a “1”, the latch
is set, when set to a “0”, the latch is reset.
The Block Lock (BL0 and BL1) bits are nonvolatile and
allow the user to select one of four levels of protection.
The X25138 is divided into four 32K-bit segments.
One, two, or all four of the segments may be protected.
That is, the user may read the segments but will be
unable to alter (write) data within the selected
segments. The partitioning is controlled as illustrated
below.
Status Register Bits
BL1 BL0
00
01
10
11
Array Addresses
Protected
None
$3000–$3FFF
$2000–$3FFF
$0000–$3FFF
7037 FRM T03
Table 1. Instruction Set
Instruction Name Instruction Format*
Operation
WREN
0000 0110
Set the Write Enable Latch (Enable Write Operations)
WRDI
0000 0100
Reset the Write Enable Latch (Disable Write Operations)
RDSR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register
READ
0000 0011
Read Data from Memory Array beginning at selected address
WRITE
0000 0010
Write Data to Memory Array beginning at Selected Address (1 to 32
Bytes)
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
7037 FRM T04
3


3Pages


X25138S8I-V 電子部品, 半導体
X25138
Figure 3. Write Enable Latch Sequence
CS
SCK
01234567
SI
HIGH IMPEDANCE
SO
7037 FRM F05
Figure 4. Byte Write Operation Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30 31
INSTRUCTION
16 BIT ADDRESS
DATA BYTE
SI
15 14 13
321076543210
HIGH IMPEDANCE
SO
7037 FRM F06
6

6 Page



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部品番号部品説明メーカ
X25138S8I-V

5MHz SPI Serial E2PROM with Block Lock PROTECTION

Xicor
Xicor


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