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X25080P-2.7 の電気的特性と機能

X25080P-2.7のメーカーはXicorです、この部品の機能は「SPI Serial E2PROM With Block LockTM Protection」です。


製品の詳細 ( Datasheet PDF )

部品番号 X25080P-2.7
部品説明 SPI Serial E2PROM With Block LockTM Protection
メーカ Xicor
ロゴ Xicor ロゴ 




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X25080P-2.7 Datasheet, X25080P-2.7 PDF,ピン配置, 機能
APPLICATION NOTE
AVA I L A B L E
X25080
AN61
8K
X25080
1K x 8 Bit
SPI Serial E2PROM With Block LockTM Protection
FEATURES
• 2MHz Clock Rate
• SPI Modes (0,0 & 1,1)
• 1K X 8 Bits
— 32 Byte Page Mode
• Low Power CMOS
— <1µA Standby Current
— <5mA Active Current
• 2.7V To 5.5V Power Supply
• Block Lock Protection
— Protect 1/4, 1/2 or all of E2PROM Array
• Built-in Inadvertent Write Protection
— Power-Up/Power-Down protection circuitry
— Write Enable Latch
— Write Protect Pin
• Self-Timed Write Cycle
— 5ms Write Cycle Time (Typical)
• High Reliability
— Endurance: 100,000 cycles
— Data Retention: 100 Years
— ESD protection: 2000V on all pins
• 8-Lead PDlP Package
• 8-Lead SOIC Package
• 14-Lead TSSOP Package
DESCRIPTION
The X25080 is a CMOS 8192-bit serial E2PROM,
internally organized as 1K x 8. The X25080 features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is con-
trolled through a chip select (CS) input, allowing any
number of devices to share the same bus.
The X25080 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25080 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts. The WP input can be used as a hardwire input
to the X25080 disabling all write attempts to the status
register, thus providing a mechanism for limiting end
user capability of altering 0, 1/4, 1/2 or all of the memory.
The X25080 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
STATUS
REGISTER
WRITE
PROTECT
LOGIC
SO
SI
SCK
CS
HOLD
COMMAND
DECODE
AND
CONTROL
LOGIC
X DECODE
LOGIC
8
8
16
1K BYTE
ARRAY
8 X 256
8 X 256
16 X 256
WRITE
CONTROL
AND
WP TIMING
LOGIC
Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc.
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
3090-1.7 6/11/96 T3/C1/D0 NS
1
32 8
Y DECODE
DATA REGISTER
3090 ILL F01
Characteristics subject to change without notice

1 Page





X25080P-2.7 pdf, ピン配列
X25080
PRINCIPLES OF OPERATION
The X25080 is a 1K x 8 E2PROM designed to interface
directly with the synchronous serial peripheral interface
(SPI) of many popular microcontroller families.
The X25080 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising SCK. CS must be LOW and the HOLD and WP
inputs must be HIGH during the entire operation. The
WP input is “Don’t Care” if WPEN is set “0”.
Table 1 contains a list of the instructions and their
opcodes. All instructions, addresses and data are trans-
ferred MSB first.
Data input is sampled on the first rising edge of SCK after
CS goes LOW. SCK is static, allowing the user to stop
the clock and then resume operations. If the clock line is
shared with other peripheral devices on the SPI bus, the
user can assert the HOLD input to place the X25080 into
a “PAUSE” condition. After releasing HOLD, the X25080
will resume operation from the point when HOLD was
first asserted.
Write Enable Latch
The X25080 contains a “write enable” latch. This latch
must be SET before a write operation will be completed
internally. The WREN instruction will set the latch and
the WRDI instruction will reset the latch. This latch is
automatically reset upon a power-up condition and after
the completion of a byte, page, or status register write
cycle.
Status Register
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
7 654 3
2 10
WPEN X X X BP1 BP0 WEL WIP
3090 PGM T02
WPEN, BP0 and BP1 are set by the WRSR instruction.
WEL and WIP are read-only and automatically set by
other operations.
The Write-In-Process (WIP) bit indicates whether the
X25080 is busy with a write operation. When set to a “1”,
a write is in progress, when set to a “0”, no write is in
progress. During a write, all other bits are set to “1”.
The Write Enable Latch (WEL) bit indicates the status of
the “write enable” latch. When set to a “1”, the latch is set,
when set to a “0”, the latch is reset.
The Block Protect (BP0 and BP1) bits are nonvolatile
and allow the user to select one of four levels of protec-
tion. The X25080 is divided into four 2048-bit segments.
One, two, or all four of the segments may be protected.
That is, the user may read the segments but will be
unable to alter (write) data within the selected segments.
The partitioning is controlled as illustrated below.
Status Register Bits
BP1 BP0
00
01
10
11
Array Addresses
Protected
None
$0300–$03FF
$0200–$03FF
$0000–$03FF
3090 PGM T03
Table 1. Instruction Set
Instruction Name Instruction Format*
Operation
WREN
0000 0110
Set the Write Enable Latch (Enable Write Operations)
WRDI
0000 0100
Reset the Write Enable Latch (Disable Write Operations)
RDSR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register
READ
0000 0011
Read Data from Memory Array beginning at selected
address
WRITE
0000 0010
Write Data to Memory Array beginning at Selected Address
(1 to 32 Bytes)
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
3090 PGM T04
3


3Pages


X25080P-2.7 電子部品, 半導体
X25080
Figure 3. Write Enable Latch Sequence
CS
SCK
01234567
SI
HIGH IMPEDANCE
SO
3090 ILL F05
Figure 4. Byte Write Operation Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30 31
INSTRUCTION
16 BIT ADDRESS
DATA BYTE
SI
15 14 13
321076543210
HIGH IMPEDANCE
SO
3090 ILL F06
6

6 Page



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部品番号部品説明メーカ
X25080P-2.7

SPI Serial E2PROM With Block LockTM Protection

Xicor
Xicor


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