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X25057P の電気的特性と機能

X25057PのメーカーはXicorです、この部品の機能は「5MHz Low Power SPI Serial E 2 PROM with IDLock Memory」です。


製品の詳細 ( Datasheet PDF )

部品番号 X25057P
部品説明 5MHz Low Power SPI Serial E 2 PROM with IDLock Memory
メーカ Xicor
ロゴ Xicor ロゴ 




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X25057P Datasheet, X25057P PDF,ピン配置, 機能
4K
X25057
512 x 8 Bit
5MHz Low Power SPI Serial E2PROM with IDLock™ Memory
FEATURES
• 5MHz Clock Rate
• IDLock™ Memory
—IDLock First or Last Page, Any 1/4 or Lower 1/2
of E2PROM Array
• Low Power CMOS
—<1µA Standby Current
—<3mA Active Current during Write
—<400µA Active Current during Read
• 1.8V to 3.6V, 2.7V-5.5V or 4.5V to 5.5V Operation
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down Protection Circuitry
—Write Enable Latch
—Write Protect Pin
• SPI Modes (0,0 & 1,1)
• 512 x 8 Bits
—16 Byte Page Mode
• Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
• High Reliability
—Endurance: 100,000 Cycles/Byte
—Data Retention: 100 Years
—ESD: 2000V on all pins
• 8-Lead MSOP Package
• 8-Lead TSSOP Package
• 8-Lead SOIC Package
• 8-Lead PDIP Package
DESCRIPTION
The X25057 is a CMOS 4K-bit serial E2PROM, internally
organized as 512 x 8. The X25057 features a Serial
Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
IDLock is a programmable locking mechanism which
allows the user to lock system ID and parametric data in
different portions of the E2PROM memory space,
ranging from as little as one page to as much as 1/2 of
the total array. The X25057 also features a WP pin that
can be used for hardwire protection of the part, disabling
all write attempts, as well as a Write Enable Latch that
must be set before a write operation can be initiated.
The X25057 utilizes Xicor’s proprietary Direct WriteTM
cell, providing a minimum endurance of 100,000 cycles
per byte and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
SI
SO
SCK
CS
COMMAND
DECODE
AND
CONTROL
LOGIC
X
DECODE
LOGIC
DATA REGISTER
Y DECODE LOGIC
16 8
32
4K E2PROM
ARRAY
(512 x 8)
WP WRITE CONTROL LOGIC
©Xicor, Inc. 1994 – 1997 Patents Pending
7033-1.1 5/8/97 T1/C0/D0 SH
1
HIGH VOLTAGE
CONTROL
7033 FRM F01
Characteristics subject to change without notice

1 Page





X25057P pdf, ピン配列
X25057
Write Enable Latch
The X25057 contains a “Write Enable” latch. This latch
must be SET before a write operation is initiated. The
WREN instruction will set the latch and the WRDI instruc-
tion will reset the latch (Figure 4). This latch is automati-
cally reset upon a power-up condition and after the
completion of a byte or page write cycle.
IDLock Memory
Xicor’s IDLock Memory provides a flexible mechanism to
store and lock system ID and parametric information.
There are seven distinct IDLock Memory areas within the
array which vary in size from one page to as much as half
of the entire array. These areas and associated address
ranges are IDLocked by writing the appropriate two byte
IDLock instruction to the device as described in Table 1
and Figure 7. Once an IDLock instruction has been com-
pleted, that IDLock setup is held in a nonvolatile Status
Register (Figure 1) until the next IDLock instruction is
issued. The sections of the memory array that are
IDLocked can be read but not written until IDLock is
removed or changed.
Figure 1. Status Register/IDLock Protection Byte
76543210
0 0 0 0 0 IDL2 IDL1 IDL0
Note: Bits [7:3] specified to be “0’s”
7038 FRM T02.1
Clock and Data Timing
Data input on the SI line is latched on the rising edge of
SCK. Data is output on the SO line by the falling edge of
SCK.
Read Sequence
When reading from the E2PROM memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25057, followed by the
16-bit address, of which the last 9 bits are used (bits
[15:9] specified to be zeroes). After the READ opcode
and address are sent, the data stored in the memory at
the selected address is shifted out on the SO line. The
data stored in memory at the next address can be read
sequentially by continuing to provide clock pulses. The
address is automatically incremented to the next higher
address after each byte of data is shifted out. When the
highest address is reached (01FFh), the address counter
rolls over to address 0000h, allowing the read cycle to be
continued indefinitely. The read operation is terminated
by taking CS HIGH. Refer to the Read Operation
Sequence illustrated in Figure 2.
Read Status Operation
If there is not a nonvolatile write in progress, the Read
Status instruction returns the ID Lock byte from the Sta-
tus Register which contains the ID Lock bits IDL2-IDL0
(Figure 1). The ID Lock bits define the ID Lock condition
(Figure 1/Table1). The other bits are reserved and will
return ’0’ when read. See Figure 3.
If a nonvolatile write is in progress, the Read Status
Instruction returns a HIGH on SO. When the nonvolatile
write cycle is completed, the status register data is read
out.
Clocking SCK is valid during a nonvolatile write in
progress, but is not necessary. If the SCK line is clocked,
the pointer to the status register is also clocked, even
though the SO pin shows the status of the nonvolatile
write operation (See Figure 3).
Write Sequence
Prior to any attempt to write data into the X25057, the
“Write Enable” latch must first be set by issuing the
WREN instruction (See Table 1 and Figure 4). CS is first
taken LOW. Then the WREN instruction is clocked into
the X25057. After all eight bits of the instruction are
transmitted, CS must then be taken HIGH. If the user
continues the write operation without taking CS HIGH
after issuing the WREN instruction, the write operation
will be ignored.
To write data to the E2PROM memory array, the user then
issues the WRITE instruction, followed by the 16 bit
address and the data to be written. Only the last 9 bits of
the address are used and bits [15:9] are specified to be
zeroes. This is minimally a thirty-two clock operation. CS
must go LOW and remain LOW for the duration of the
operation. The host may continue to write up to 16 bytes
of data to the X25057. The only restriction is the 16 bytes
must reside on the same page. If the address counter
reaches the end of the page and the clock continues, the
counter will “roll over” to the first address of the page and
overwrite any data that may have been previously written.
For a byte or page write operation to be completed, CS
can only be brought HIGH after bit 0 of the last data byte
to be written is clocked in. If it is brought HIGH at any
other time, the write operation will not be completed.
Refer to Figures 5 and 6 for detailed illustration of the
write sequences and time frames in which CS going
HIGH are valid.
3


3Pages


X25057P 電子部品, 半導体
X25057
Figure 4. WREN/WRDI Sequence
CS
SCK
SI
01234567
INSTRUCTION
(1 BYTE)
HIGH IMPEDANCE
SO
Figure 5. Byte Write Operation Sequence
CS
7033 FRM F05.1
SCK
SI
0123456789
20 21 22 23 24 25 26 27 28 29 30 31
WRITE INSTRUCTION
(1 BYTE)
BYTE ADDRESS (2 BYTE)
15 14
3210
DATA BYTE
76543210
HIGH IMPEDANCE
SO
7033 FRM F06
6

6 Page



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共有リンク

Link :


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X25057

5MHz Low Power SPI Serial E 2 PROM with IDLock Memory

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X25057M

5MHz Low Power SPI Serial E 2 PROM with IDLock Memory

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X25057M-1.8

5MHz Low Power SPI Serial E 2 PROM with IDLock Memory

Xicor
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X25057M-2.7

5MHz Low Power SPI Serial E 2 PROM with IDLock Memory

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Xicor


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