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X24F016P の電気的特性と機能

X24F016PのメーカーはXicorです、この部品の機能は「SerialFlash TM Memory with Block Lock TM Protection」です。


製品の詳細 ( Datasheet PDF )

部品番号 X24F016P
部品説明 SerialFlash TM Memory with Block Lock TM Protection
メーカ Xicor
ロゴ Xicor ロゴ 




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X24F016P Datasheet, X24F016P PDF,ピン配置, 機能
APPLICATION NOTE
A V A I LABLE
AN76 • AN78 • AN81 • AN87
64K/32K/16K
X24F064/032/016
8K/4K/2K x 8 Bit
SerialFlashTM Memory with Block LockTM Protection
FEATURES
1.8V to 3.6V or 5V “Univolt” Read and
Program Power Supply Versions
Low Power CMOS
—Active Read Current Less Than 1mA
—Active Program Current Less Than 3mA
—Standby Current Less Than 1µA
Internally Organized 8K/4K/2K x 8
New Programmable Block Lock Protection
—Software Write Protection
—Programmable hardware Write Protect
Block Lock (0, 1/4, 1/2, or all of the Flash
Memory array)
2 Wire Serial Interface
Bidirectional Data Transfer Protocol
32 Byte Sector Programming
Self Timed Program Cycle
—Typical Programming Time of 5ms
Per Sector
High Reliability
—Endurance: 100,000 cycles per byte
—Data Retention: 100 Years
Available Packages
—8-Lead PDIP
—8-Lead SOIC (JEDEC)
—14-Lead TSSOP (X24F032/016)
—20-Lead TSSOP (X24F064)
DESCRIPTION
The X24F064/032/016 is a CMOS SerialFlash
Memory Family, internally organized 8K/4K/2K x 8.
The family features a serial interface and software
protocol allowing operation on a simple two wire bus.
Device select inputs (S0, S1, S2) allow up to eight
devices to share a common two wire bus.
A Program Protect Register accessed at the highest
address location, provides three new programming
protection features: Software Programming Protection,
Block Lock Protection, and Hardware Programming
Protection. The Software Programming Protection
feature prevents any nonvolatile writes to the device
until the WEL bit in the program protect register is set.
The Block LockTM Protection feature allows the user to
individually protect four blocks of the array by program-
ming two bits in the programming protect register. The
Programmable Hardware Program Protect feature
allows the user to install each device with PP tied to
VCC, program the entire memory array in place, and
then enable the hardware programming protection by
programming a PPEN bit in the program protect
register. After this, selected blocks of the array,
including the program protect register itself, are
permanently protected from being programmed.
FUNCTIONAL DIAGRAM
SDA
SCL
DATA REGISTER
SECTOR DECODE LOGIC
32 8
S0/S0
S1/S1
S2/S2
COMMAND
DECODE
AND CONTROL
LOGIC
X
DECODE
LOGIC
PROGRAM
PROTECT
REGISTER
SECTORED
MEMORY
ARRAY
PP
PROGRAMMING
CONTROL LOGIC
SerialFlashMemory and Block Lock
Protection are trademarks of Xicor, Inc.
©Xicor, 1995, 1996 Patents Pending
6686-3.8 8/29/96 T3/C0/D0 SH
1
HIGH VOLTAGE
CONTROL
6686 ILL F01.5
Characteristics subject to change without notice

1 Page





X24F016P pdf, ピン配列
X24F064/032/016
DEVICE OPERATION
The X24F064/032/016 supports a bidirectional bus ori-
ented protocol. The protocol defines any device that
sends data onto the bus as a transmitter, and the re-
ceiving device as the receiver. The device controlling
the transfer is a master and the device being controlled
is the slave. The master will always initiate data trans-
fers, and provide the clock for both transmit and receive
operations. Therefore, the X24F064/032/016 will be
considered a slave in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24F064/032/016 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition has
been met.
Figure 1. Data Validity
SCL
SDA
DATA STABLE DATA
CHANGE
6686 ILL F04
Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (2.7V)
(6) tPR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the
device requires to perform the internal program operation.
Figure 2. Definition of Start and Stop
SCL
SDA
START BIT
STOP BIT
6686 ILL F05
3


3Pages


X24F016P 電子部品, 半導体
X24F064/032/016
Flow 1. ACK Polling Sequence
PROGRAM OPERATION
COMPLETED
ENTER ACK POLLING
ISSUE
START
ISSUE SLAVE
ADDRESS AND R/W = 0
ACK
NO
RETURNED?
YES
NEXT
OPERATION
A WRITE?
YES
NO
ISSUE SECTOR
ADDRESS
ISSUE STOP
ISSUE STOP
PROCEED
PROCEED
6686 ILL F09.1
After the receipt of each byte, the five low order ad-
dress bits are internally incremented by one. The high
order bits of the sector address remain constant. If the
master should transmit more or less than 32 bytes prior
to generating the stop condition, the contents of the
sector cannot be guaranteed. All inputs are disabled
until completion of the internal program cycle. Refer to
Figure 5 for the address, acknowledge and data trans-
fer sequence.
Acknowledge Polling
The Max Write Cycle Time can be significantly reduced
using Acknowledge Polling. To initiate Acknowledge
Polling, the master issues a start condition followed by
the Slave Address Byte for a write or read operation. If
the device is still busy with the high voltage cycle, then
no ACK will be returned. If the device has completed
the write operation, an ACK will be returned and the
host can then proceed with the read or write operation.
Refer to Flow 1.
READ OPERATIONS
Read operations are initiated in the same manner as
program operations with the exception that the R/W bit
of the slave address is set HIGH. There are three basic
read operations: current address read, random read
and sequential read.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read op-
eration, the master must either issue a stop condition
during the ninth cycle or hold SDA HIGH during the
ninth clock cycle and then issue a stop condition.
6

6 Page



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共有リンク

Link :


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