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X24C45SI の電気的特性と機能

X24C45SIのメーカーはXicorです、この部品の機能は「Serial AUTOSTORE NOVRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 X24C45SI
部品説明 Serial AUTOSTORE NOVRAM
メーカ Xicor
ロゴ Xicor ロゴ 




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X24C45SI Datasheet, X24C45SI PDF,ピン配置, 機能
APPLICATION NOTES
AVA I L A B L E
AN3 • AN7 • AN8 • AN15 • AN16 • AN25 • AN29
X24C45• AN30 • AN35 • AN36 • AN39 • AN56 • AN69
256 Bit
X24C45
Serial AUTOSTORE™ NOVRAM
16 x 16 Bit
FEATURES
AUTOSTORE™ NOVRAM
—Automatically Performs a Store Operation
Upon Loss of VCC
Single 5 Volt Supply
Ideal for use with Single Chip Microcomputers
—Minimum I/O Interface
—Serial Port Compatible (COPS™, 8051)
—Easily Interfaced to Microcontroller Ports
Software and Hardware Control of Nonvolatile
Functions
Auto Recall on Power-Up
TTL and CMOS Compatible
Low Power Dissipation
—Active Current: 10mA
—Standby Current: 50µA
8-Lead PDIP and 8-Lead SOIC Packages
High Reliability
—Store Cycles: 1,000,000
—Data Retention: 100 Years
FUNCTIONAL DIAGRAM
DESCRIPTION
The Xicor X24C45 is a serial 256 bit NOVRAM featuring
a static RAM configured 16 x 16, overlaid bit-by-bit with
a nonvolatile E2PROM array. The X24C45 is fabricated
with Xicor’s Advanced CMOS Floating Gate technology.
The Xicor NOVRAM design allows data to be transferred
between the two memory arrays by means of software
commands or external hardware inputs. A store opera-
tion (RAM data to E2PROM) is completed in 5ms or less
and a recall operation (E2PROM data to RAM) is com-
pleted in 2µs or less.
The X24C45 also includes the AUTOSTORE feature, a
user selectable feature that automatically performs a
store operation when VCC falls below a preset threshold.
Xicor NOVRAMs are designed for unlimited write opera-
tions to RAM, either from the host or recalls from E2PROM
and a minimum 1,000,000 store operations. Inherent data
retention is specified to be greater than 100 years.
NONVOLATILE
E2PROM
ROW
DECODE
STATIC
RAM
256-BIT
CONTROL
LOGIC
RECALL (6)
AS (7)
CE (1)
DI (3)
SK (2)
INSTRUCTION
REGISTER
INSTRUCTION
DECODE
COLUMN
DECODE
4-BIT
COUNTER
AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc.
COPS is a trademark of National Semiconductor Corp.
© Xicor, Inc. 1991, 1995, 1996 Patents Pending
3833-1.5 6/10/96 T3/C3/D0 NS
1
DO (4)
3833 FHD F01
Characteristics subject to change without notice

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X24C45SI pdf, ピン配列
X24C45
DEVICE OPERATION
The X24C45 contains an 8-bit instruction register. It is
accessed via the DI input, with data being clocked in on
the rising edge of SK. CE must be HIGH during the entire
data transfer operation.
Table 1. contains a list of the instructions and their
operation codes. The most significant bit (MSB) of all
instructions is a logic one (HIGH), bits 6 through 3 are
either RAM address bits (A) or don’t cares (X) and bits
2 through 0 are the operation codes. The X24C45
requires the instruction to be shifted in with the MSB first.
After CE is HIGH, the X24C45 will not begin to interpret
the data stream until a logic “1” has been shifted in on DI.
Therefore, CE may be brought HIGH with SK running
and DI LOW. DI must then go HIGH to indicate the start
condition of an instruction before the X24C45 will begin
any action.
In addition, the SK clock is totally static. The user can
completely stop the clock and data shifting will be
stopped. Restarting the clock will resume shifting of
data.
RCL and RECALL
Either a software RCL instruction or a LOW on the
RECALL input will initiate a transfer of E2PROM data
into RAM. This software or hardware recall operation
sets an internal “previous recall” latch. This latch is reset
upon power-up and must be intentionally set by the user
to enable any write or store operations. Although a recall
operation is performed upon power-up, the previous
recall latch is not set by this operation.
WRDS and WREN
Internally the X24C45 contains a “write enable” latch. This
latch must be set for either writes to the RAM or store
operations to the E2PROM. The WREN instruction sets
the latch and the WRDS instruction resets the latch,
disabling both RAM writes and E2PROM stores, effec-
tively protecting the nonvolatile data from corruption. The
write enable latch is automatically reset on power-up.
STO
The software STO instruction will initiate a transfer of
data from RAM to E2PROM. In order to safeguard
against unwanted store operations, the following condi-
tions must be true:
• STO instruction issued.
• The internal “write enable” latch must be set
(WREN instruction issued).
• The “previous recall” latch must be set (either a
software or hardware recall operation).
Once the store cycle is initiated, all other device func-
tions are inhibited. Upon completion of the store cycle,
the write enable latch is reset. Refer to Figure 4 for a
state diagram description of enabling/disabling condi-
tions for store operations.
TABLE 1. INSTRUCTION SET
Instruction
WRDS (Figure 3)
STO (Figure 3)
ENAS
WRITE (Figure 2)
WREN (Figure 3)
RCL (Figure 3)
READ (Figure 1)
Format, I2 I1 I0
1XXXX000
1XXXX001
1XXXX010
1AAAA011
1XXXX100
1XXXX101
1AAAA11X
X = Don’t Care
A = Address
Operation
Reset Write Enable Latch (Disables Writes and Stores)
Store RAM Data in E2PROM
Enable AUTOSTORE Feature
Write Data into RAM Address AAAA
Set Write Enable Latch (Enables Writes and Stores)
Recall E2PROM Data into RAM
Read Data from RAM Address AAAA
3833 PGM T11
3


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X24C45SI 電子部品, 半導体
X24C45
Figure 4. X24C45 State Diagram
POWER
ON
POWER
OFF
POWER-UP
RECALL
RAM
READ
ENABLED
RAM READ
AUTOSTORE
POWER DOWN
STO OR
WRDS CMD
RCL COMMAND
OR RECALL
RAM
READ
ENABLED
RAM READ
RAM READ
OR WRITE
WREN
COMMAND
RAM
READ & WRITE
ENABLED
STORE ENABLED
AUTOSTORE
ENABLED
STO OR
WRDS CMD
WREN
COMMAND
ENAS COMMAND
RAM
READ & WRITE
ENABLED
STORE
ENABLED
RAM READ
OR WRITE
3833 FHD F12.1
6

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
X24C45S

Serial AUTOSTORE NOVRAM

Xicor
Xicor
X24C45SI

Serial AUTOSTORE NOVRAM

Xicor
Xicor
X24C45SM

Serial AUTOSTORE NOVRAM

Xicor
Xicor


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