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X24C16S8-3 の電気的特性と機能

X24C16S8-3のメーカーはXicorです、この部品の機能は「Serial E2PROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 X24C16S8-3
部品説明 Serial E2PROM
メーカ Xicor
ロゴ Xicor ロゴ 




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X24C16S8-3 Datasheet, X24C16S8-3 PDF,ピン配置, 機能
XPr2e4liCm1in6ary Information
16K
X24C16
Serial E2PROM
2048 x 8 Bit
FEATURES
2.7V to 5.5V Power Supply
Low Power CMOS
—Active Read Current Less Than 1 mA
—Active Write Current Less Than 3 mA
—Standby Current Less Than 50 µA
Internally Organized 2048 x 8
2 Wire Serial Interface
—Bidirectional Data Transfer Protocol
Sixteen Byte Page Write Mode
—Minimizes Total Write Time Per Byte
Self Timed Write Cycle
—Typical Write Cycle Time of 5 ms
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
8 Pin Mini-DIP, 8 Pin SOIC and 14 Pin SOIC
Packages
DESCRIPTION
The X24C16 is a CMOS 16,384 bit serial E2PROM,
internally organized 2048 X 8. The X24C16 features a
serial interface and software protocol allowing operation
on a simple two wire bus.
The X24C16 is fabricated with Xicor’s advanced CMOS
Textured Poly Floating Gate Technology.
The X24C16 utilizes Xicor’s proprietary Direct WriteTM
cell providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
(8) VCC
(4) VSS
(7) TEST
(5) SDA
START
STOP
LOGIC
START CYCLE
H.V. GENERATION
TIMING
& CONTROL
(6) SCL
(3) A2
(2) A1
(1) A0
SLAVE ADDRESS
REGISTER
+COMPARATOR
CONTROL
LOGIC
LOAD
INC
WORD
ADDRESS
COUNTER
R/W
DOUT
ACK
PIN
XDEC
E2PROM
128 X 128
YDEC
8
CK DATA REGISTER DOUT
3840 FHD F01
© Xicor, 1991 Patents Pending
3840-1.1 7/29/96 T1/C0/D0 SH
1 Characteristics subject to change without notice

1 Page





X24C16S8-3 pdf, ピン配列
X24C16
DEVICE OPERATION
The X24C16 supports a bidirectional bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master will always initiate data transfers, and provide
the clock for both transmit and receive operations.
Therefore, the X24C16 will be considered a slave in all
applications.
Figure 1. Data Validity
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are re-
served for indicating start and stop conditions. Refer to
Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24C16 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
SCL
SDA
DATA STABLE DATA
CHANGE
3840 FHD F06
3


3Pages


X24C16S8-3 電子部品, 半導体
X24C16
Page Write
The X24C16 is capable of a sixteen byte page write
operation. It is initiated in the same manner as the byte
write operation, but instead of terminating the write cycle
after the first data word is transferred, the master can
transmit up to fifteen more words. After the receipt of
each word, the X24C16 will respond with an acknowl-
edge.
After the receipt of each word, the four low order address
bits are internally incremented by one. The high order
seven bits of the address remain constant. If the master
should transmit more than sixteen words prior to gener-
ating the stop condition, the address counter will “roll
over” and the previously written data will be overwritten.
As with the byte write operation, all inputs are disabled
until completion of the internal write cycle. Refer to
Figure 6 for the address, acknowledge and data transfer
sequence.
Acknowledge Polling
The disabling of the inputs can be used to take advan-
tage of the typical 5 ms write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation the X24C16 initiates the internal write cycle.
ACK polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the X24C16 is still busy with the
write operation no ACK will be returned. If the X24C16
has completed the write operation an ACK will be
returned and the host can then proceed with the next
read or write operation. Refer to Flow 1.
Flow 1. ACK Polling Sequence
WRITE OPERATION
COMPLETED
ENTER ACK POLLING
ISSUE
START
ISSUE SLAVE
ADDRESS AND R/W = 0
ACK
NO
RETURNED?
YES
NEXT
OPERATION
A WRITE?
YES
NO
ISSUE BYTE
ADDRESS
ISSUE STOP
ISSUE STOP
PROCEED
PROCEED
3840 FHD F11
Figure 6. Page Write
S
T
BUS ACTIVITY: A
MASTER
R
T
SDA LINE
S
BUS ACTIVITY:
X24C16
SLAVE
ADDRESS
WORD
ADDRESS (n)
AA
CC
KK
DATA n
DATA n+1
AA
CC
KK
NOTE: In this example n = xxxx 000 (B); x = 1 or 0
DATA n+15
S
T
O
P
P
A
C
K
3840 FHD F12
6

6 Page



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共有リンク

Link :


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X24C16S8-3

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