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XCS20XL PDF Data sheet ( 特性 )

部品番号 XCS20XL
部品説明 Spartan and Spartan-XL Families Field Programmable Gate Arrays
メーカ Xilinx
ロゴ Xilinx ロゴ 



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XCS20XL Datasheet, XCS20XL PDF,ピン配置, 機能
0
R Spartan and Spartan-XL Families
Field Programmable Gate Arrays
DS060 (v1.6) September 19, 2001
0 0 Product Specification
Introduction
The Spartanand the Spartan-XL families are a high-vol-
ume production FPGA solution that delivers all the key
requirements for ASIC replacement up to 40,000 gates.
These requirements include high performance, on-chip
RAM, core solutions and prices that, in high volume,
approach and in many cases are equivalent to mask pro-
grammed ASIC devices.
The Spartan series is the result of more than 14 years of
FPGA design experience and feedback from thousands of
customers. By streamlining the Spartan series feature set,
leveraging advanced process technologies and focusing on
total cost management, the Spartan series delivers the key
features required by ASIC and other high-volume logic
users while avoiding the initial cost, long development
cycles and inherent risk of conventional ASICs. The Spar-
tan and Spartan-XL families in the Spartan series have ten
members, as shown in Table 1.
System level features
- Available in both 5V and 3.3V versions
- On-chip SelectRAMmemory
- Fully PCI compliant
- Full readback capability for program verification
and internal node observability
- Dedicated high-speed carry logic
- Internal 3-state bus capability
- Eight global low-skew clock or signal networks
- IEEE 1149.1-compatible Boundary Scan logic
- Low cost plastic packages available in all densities
- Footprint compatibility in common packages
Fully supported by powerful Xilinx development system
- Foundation Series: Integrated, shrink-wrap
software
- Alliance Series: Dozens of PC and workstation
third party development systems supported
- Fully automatic mapping, placement and routing
Spartan and Spartan-XL Features
Note: The Spartan series devices described in this data
sheet include the 5V Spartan family and the 3.3V
Spartan-XL family. See the separate data sheet for the 2.5V
Spartan-II family.
First ASIC replacement FPGA for high-volume
production with on-chip RAM
Density up to 1862 logic cells or 40,000 system gates
Streamlined feature set based on XC4000 architecture
System performance beyond 80 MHz
Broad set of AllianceCOREand LogiCORE
predefined solutions available
Unlimited reprogrammability
Low cost
Additional Spartan-XL Features
3.3V supply for low power with 5V tolerant I/Os
Power down input
Higher performance
Faster carry logic
More flexible high-speed clock network
Latch capability in Configurable Logic Blocks
Input fast capture latch
Optional mux or 2-input function generator on outputs
12 mA or 24 mA output drive
5V and 3.3V PCI compliant
Enhanced Boundary Scan
Express Mode configuration
Chip scale packaging
Table 1: Spartan and Spartan-XL Field Programmable Gate Arrays
Device
Max
Logic System
Typical
Gate Range
Cells Gates (Logic and RAM)(1)
CLB
Matrix
Max.
Total
Total No. of Avail. Distributed
CLBs Flip-flops User I/O RAM Bits
XCS05 and XCS05XL 238 5,000
2,000-5,000
10 x 10 100
360
77
3,200
XCS10 and XCS10XL 466 10,000
3,000-10,000
14 x 14 196
616
112
6,272
XCS20 and XCS20XL 950 20,000
7,000-20,000
20 x 20 400
1,120
160
12,800
XCS30 and XCS30XL 1368 30,000
10,000-30,000 24 x 24 576
1,536
192
18,432
XCS40 and XCS40XL 1862 40,000
13,000-40,000 28 x 28 784
2,016
224
25,088
Notes:
1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS060 (v1.6) September 19, 2001
Product Specification
www.xilinx.com
1-800-255-7778
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