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XCS20XL の電気的特性と機能

XCS20XLのメーカーはXilinxです、この部品の機能は「Spartan and Spartan-XL Families Field Programmable Gate Arrays」です。


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部品番号 XCS20XL
部品説明 Spartan and Spartan-XL Families Field Programmable Gate Arrays
メーカ Xilinx
ロゴ Xilinx ロゴ 




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XCS20XL Datasheet, XCS20XL PDF,ピン配置, 機能
0
R Spartan and Spartan-XL Families
Field Programmable Gate Arrays
DS060 (v1.6) September 19, 2001
0 0 Product Specification
Introduction
The Spartanand the Spartan-XL families are a high-vol-
ume production FPGA solution that delivers all the key
requirements for ASIC replacement up to 40,000 gates.
These requirements include high performance, on-chip
RAM, core solutions and prices that, in high volume,
approach and in many cases are equivalent to mask pro-
grammed ASIC devices.
The Spartan series is the result of more than 14 years of
FPGA design experience and feedback from thousands of
customers. By streamlining the Spartan series feature set,
leveraging advanced process technologies and focusing on
total cost management, the Spartan series delivers the key
features required by ASIC and other high-volume logic
users while avoiding the initial cost, long development
cycles and inherent risk of conventional ASICs. The Spar-
tan and Spartan-XL families in the Spartan series have ten
members, as shown in Table 1.
System level features
- Available in both 5V and 3.3V versions
- On-chip SelectRAMmemory
- Fully PCI compliant
- Full readback capability for program verification
and internal node observability
- Dedicated high-speed carry logic
- Internal 3-state bus capability
- Eight global low-skew clock or signal networks
- IEEE 1149.1-compatible Boundary Scan logic
- Low cost plastic packages available in all densities
- Footprint compatibility in common packages
Fully supported by powerful Xilinx development system
- Foundation Series: Integrated, shrink-wrap
software
- Alliance Series: Dozens of PC and workstation
third party development systems supported
- Fully automatic mapping, placement and routing
Spartan and Spartan-XL Features
Note: The Spartan series devices described in this data
sheet include the 5V Spartan family and the 3.3V
Spartan-XL family. See the separate data sheet for the 2.5V
Spartan-II family.
First ASIC replacement FPGA for high-volume
production with on-chip RAM
Density up to 1862 logic cells or 40,000 system gates
Streamlined feature set based on XC4000 architecture
System performance beyond 80 MHz
Broad set of AllianceCOREand LogiCORE
predefined solutions available
Unlimited reprogrammability
Low cost
Additional Spartan-XL Features
3.3V supply for low power with 5V tolerant I/Os
Power down input
Higher performance
Faster carry logic
More flexible high-speed clock network
Latch capability in Configurable Logic Blocks
Input fast capture latch
Optional mux or 2-input function generator on outputs
12 mA or 24 mA output drive
5V and 3.3V PCI compliant
Enhanced Boundary Scan
Express Mode configuration
Chip scale packaging
Table 1: Spartan and Spartan-XL Field Programmable Gate Arrays
Device
Max
Logic System
Typical
Gate Range
Cells Gates (Logic and RAM)(1)
CLB
Matrix
Max.
Total
Total No. of Avail. Distributed
CLBs Flip-flops User I/O RAM Bits
XCS05 and XCS05XL 238 5,000
2,000-5,000
10 x 10 100
360
77
3,200
XCS10 and XCS10XL 466 10,000
3,000-10,000
14 x 14 196
616
112
6,272
XCS20 and XCS20XL 950 20,000
7,000-20,000
20 x 20 400
1,120
160
12,800
XCS30 and XCS30XL 1368 30,000
10,000-30,000 24 x 24 576
1,536
192
18,432
XCS40 and XCS40XL 1862 40,000
13,000-40,000 28 x 28 784
2,016
224
25,088
Notes:
1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS060 (v1.6) September 19, 2001
Product Specification
www.xilinx.com
1-800-255-7778
1

1 Page





XCS20XL pdf, ピン配列
R Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan series devices achieve high-performance, low-cost
operation through the use of an advanced architecture and
semiconductor technology. Spartan and Spartan-XL
devices provide system clock rates exceeding 80 MHz and
internal performance in excess of 150 MHz. In contrast to
other FPGA devices, the Spartan series offers the most
cost-effective solution while maintaining leading-edge per-
formance. In addition to the conventional benefit of high vol-
ume programmable logic solutions, Spartan series FPGAs
also offer on-chip edge-triggered single-port and dual-port
RAM, clock enables on all flip-flops, fast carry logic, and
many other features.
The Spartan/XL families leverage the highly successful
XC4000 architecture with many of that familys features and
benefits. Technology advancements have been derived
from the XC4000XLA process developments.
Logic Functional Description
The Spartan series uses a standard FPGA structure as
shown in Figure 1, page 2. The FPGA consists of an array
of configurable logic blocks (CLBs) placed in a matrix of
routing channels. The input and output of signals is
achieved through a set of input/output blocks (IOBs) forming
a ring around the CLBs and routing channels.
CLBs provide the functional elements for implementing
the users logic.
IOBs provide the interface between the package pins
and internal signal lines.
Routing channels provide paths to interconnect the
inputs and outputs of the CLBs and IOBs.
The functionality of each circuit block is customized during
configuration by programming internal static memory cells.
The values stored in these memory cells determine the
logic functions and interconnections implemented in the
FPGA.
Configurable Logic Blocks (CLBs)
The CLBs are used to implement most of the logic in an
FPGA. The principal CLB elements are shown in the simpli-
fied block diagram in Figure 2. There are three look-up
tables (LUT) which are used as logic function generators,
two flip-flops and two groups of signal steering multiplexers.
There are also some more advanced features provided by
the CLB which will be covered in the Advanced Features
Description, page 13.
Function Generators
Two 16 x 1 memory look-up tables (F-LUT and G-LUT) are
used to implement 4-input function generators, each offer-
ing unrestricted logic implementation of any Boolean func-
tion of up to four independent input signals (F1 to F4 or G1
to G4). Using memory look-up tables the propagation delay
is independent of the function implemented.
A third 3-input function generator (H-LUT) can implement
any Boolean function of its three inputs. Two of these inputs
are controlled by programmable multiplexers (see box "A" of
Figure 2). These inputs can come from the F-LUT or G-LUT
outputs or from CLB inputs. The third input always comes
from a CLB input. The CLB can, therefore, implement cer-
tain functions of up to nine inputs, like parity checking. The
three LUTs in the CLB can also be combined to do any arbi-
trarily defined Boolean function of five inputs.
DS060 (v1.6) September 19, 2001
Product Specification
www.xilinx.com
1-800-255-7778
3


3Pages


XCS20XL 電子部品, 半導体
Spartan and Spartan-XL Families Field Programmable Gate Arrays
R
DIN GSR
H1
C1
C2
SR
C3
C4
EC
Multiplexer Controlled
by Configuration Program
DS060_04_081100
Figure 4: CLB Control Signal Interface
The four internal control signals are:
EC: Enable Clock
SR: Asynchronous Set/Reset or H function generator
Input 0
DIN: Direct In or H function generator Input 2
H1: H function generator Input 1.
Input/Output Blocks (IOBs)
User-configurable input/output blocks (IOBs) provide the
interface between external package pins and the internal
logic. Each IOB controls one package pin and can be con-
figured for input, output, or bidirectional signals. Figure 6
shows a simplified functional block diagram of the Spar-
tan/XL IOB.
D
CK
EC
Vcc
SD
DQ
Q
RD
Multiplexer Controlled
by Configuration Program
DS060_05_041901
Figure 5: IOB Flip-Flop/Latch Functional Block
Diagram
IOB Input Signal Path
The input signal to the IOB can be configured to either go
directly to the routing channels (via I1 and I2 in Figure 6) or
to the input register. The input register can be programmed
as either an edge-triggered flip-flop or a level-sensitive
latch. The functionality of this register is shown in Table 3,
and a simplified block diagram of the register can be seen in
Figure 5.
Table 3: Input Register Functionality
Mode
CK EC D Q
Power-Up or
GSR
X X X SR
Flip-Flop
1* D D
0 XXQ
Latch
1 1* X Q
0 1* D D
Both
X 0 XQ
Legend:
X Dont care.
Rising edge (clock not inverted).
SR Set or Reset value. Reset is default.
0* Input is Low or unconnected (default
value)
1* Input is High or unconnected (default
value)
6
www.xilinx.com
DS060 (v1.6) September 19, 2001
1-800-255-7778
Product Specification

6 Page



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部品番号部品説明メーカ
XCS20XL

Spartan and Spartan-XL Families Field Programmable Gate Arrays

Xilinx
Xilinx


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