XM28C020PI-12 Datasheet PDF - Xicor Inc.
| Part Number | XM28C020PI-12 | |
| Description | 5 Volt/ Byte Alterable E2PROM | |
| Manufacturers | Xicor Inc. | |
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XM28C020
2 Megabit Module
XM28C020
5 Volt, Byte Alterable E2PROM
256K x 8 Bit
TYPICAL FEATURES
• High Density 2 Megabit (256K x 8) Module
• Access Time of 150ns at –55°C to +125°C
• Base Memory Component: Xicor X28C513
• Pinout conforms to JEDEC Standard for
2 Megabit E2PROM
• Fast Write Cycle Times
—128 Byte Page Write
—Byte or Page Write Cycle: 5ms Typical
—Complete Memory Rewrite: 10 Seconds
• Early End of Write Detection
—DATA Polling
—Toggle Bit Polling
• Software Data Protection
• Three Temperature Ranges
—Commercial: 0°C to +75°C
—Industrial: –40° to +85°C
—Military: –55° to +125°C
• High Rel Module
—100% MIL-STD-883 Compliant Components
• Endurance: 100,000 Cycles
FUNCTIONAL DIAGRAM
X28C513
A0–A15
I/O0–I/O7
OE
WE
CE
A0–A15
I/O0–I/O7
OE
WE
CE
A16
A17
X28C513
A0–A15
I/O0–I/O7
OE
WE
CE
© Xicor, Inc. 1991, 1995, 1996 Patents Pending
3872-1.9 6/18/97 T1/C0/D0 SH
DESCRIPTION
The XM28C020 is a high density 2 Megabit E2PROM
comprised of four X28C513 LCCs mounted on a co-fired
multilayered ceramic substrate. Individual components
are 100% tested prior to assembly in module form and
then 100% tested after assembly.
The XM28C020 is configured 256K x 8 bit. The module
supports a 128-byte page write operation. This com-
bined with DATA Polling or Toggle Bit Polling, effectively
provides a 39µs/byte write cycle, enabling the entire
array to be rewritten in 10 seconds.
The XM28C020 provides the same high endurance and
data retention as the X28C513.
X28C513
A0–A15
I/O0–I/O7
OE
WE
CE
X28C513
A0–A15
I/O0–I/O7
OE
WE
CE
PIN CONFIGURATION
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 25
XM28C020
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
VCC
WE
A17
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/04
I/O3
3872 FHD F01
1
3872 FHD F02
Characteristics subject to change without notice
|
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XM28C020
THE TOGGLE BIT I/O6
Figure 4. Toggle Bit Bus Sequence
LAST
WE WRITE
CE
OE
I/O6
VOH
*
VOL
* Beginning and ending state of I/O6 will vary.
Figure 5. Toggle Bit Software Flow
LAST WRITE
LOAD ACCUM
FROM ADDR n
COMPARE
ACCUM WITH
ADDR n
HIGH Z
*
READY
3872 FHD F12
The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple XM28C020 memories that is frequently up-
dated. The timing diagram in Figure 4 illustrates the
sequence of events on the bus. The software flow
diagram in Figure 5 illustrates a method for testing the
Toggle Bit.
COMPARE
OK?
YES
READY
NO
3872 FHD F13
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for XM28C020PI-12 electronic component. |
| Information | Total 16 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ XM28C020PI-12.PDF Datasheet ] | |
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