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XM28C020P-12 の電気的特性と機能

XM28C020P-12のメーカーはXicor Inc.です、この部品の機能は「5 Volt/ Byte Alterable E2PROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 XM28C020P-12
部品説明 5 Volt/ Byte Alterable E2PROM
メーカ Xicor Inc.
ロゴ Xicor Inc. ロゴ 




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XM28C020P-12 Datasheet, XM28C020P-12 PDF,ピン配置, 機能
XM28C020
2 Megabit Module
XM28C020
5 Volt, Byte Alterable E2PROM
256K x 8 Bit
TYPICAL FEATURES
High Density 2 Megabit (256K x 8) Module
Access Time of 150ns at –55°C to +125°C
Base Memory Component: Xicor X28C513
Pinout conforms to JEDEC Standard for
2 Megabit E2PROM
Fast Write Cycle Times
—128 Byte Page Write
—Byte or Page Write Cycle: 5ms Typical
—Complete Memory Rewrite: 10 Seconds
Early End of Write Detection
DATA Polling
—Toggle Bit Polling
Software Data Protection
Three Temperature Ranges
—Commercial: 0°C to +75°C
—Industrial: –40° to +85°C
—Military: –55° to +125°C
High Rel Module
—100% MIL-STD-883 Compliant Components
Endurance: 100,000 Cycles
FUNCTIONAL DIAGRAM
X28C513
A0–A15
I/O0–I/O7
OE
WE
CE
A0–A15
I/O0–I/O7
OE
WE
CE
A16
A17
X28C513
A0–A15
I/O0–I/O7
OE
WE
CE
© Xicor, Inc. 1991, 1995, 1996 Patents Pending
3872-1.9 6/18/97 T1/C0/D0 SH
DESCRIPTION
The XM28C020 is a high density 2 Megabit E2PROM
comprised of four X28C513 LCCs mounted on a co-fired
multilayered ceramic substrate. Individual components
are 100% tested prior to assembly in module form and
then 100% tested after assembly.
The XM28C020 is configured 256K x 8 bit. The module
supports a 128-byte page write operation. This com-
bined with DATA Polling or Toggle Bit Polling, effectively
provides a 39µs/byte write cycle, enabling the entire
array to be rewritten in 10 seconds.
The XM28C020 provides the same high endurance and
data retention as the X28C513.
X28C513
A0–A15
I/O0–I/O7
OE
WE
CE
X28C513
A0–A15
I/O0–I/O7
OE
WE
CE
PIN CONFIGURATION
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 25
XM28C020
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
VCC
WE
A17
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/04
I/O3
3872 FHD F01
1
3872 FHD F02
Characteristics subject to change without notice

1 Page





XM28C020P-12 pdf, ピン配列
XM28C020
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This 2-line control architecture elimi-
nates bus contention in a system environment. The data
bus will be in a high impedance state when either OE or
CE is HIGH.
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The XM28C020 supports both a
CE and WE controlled write cycle. That is, the address
is latched by the falling edge of either CE or WE,
whichever occurs last. Similarly, the data is latched
internally by the rising edge of either CE or WE, which-
ever occurs first. A byte write operation, once initiated,
will automatically continue to completion, typically within
5ms (see Note 4).
Page Write Operation
The page write feature of the XM28C020 allows the
entire memory to be written in 10 seconds. Page write
allows two to 128 bytes of data to be consecutively
written to the XM28C020 prior to the commencement of
the internal programming cycle. The host can fetch data
from another device within the system during a page
write operation (change the source address), but the
page address (A7 through A17) for each subsequent
valid write cycle to the part during this operation must be
the same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to 127 bytes in the same
manner as the first byte was written. Each successive
byte load cycle, started by the WE HIGH to LOW
transition, must begin within 100µs of the falling edge of
the preceding WE. If a subsequent WE HIGH to LOW
transition is not detected within 100µs, the internal
automatic programming cycle will commence. There is
no page write window limitation. Effectively the page
write window is infinitely wide, so long as the host
continues to access the device within the byte load cycle
time of 100µs.
Write Operation Status Bits
The XM28C020 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
I/O DP TB 5 4 3 2 1 0
RESERVED
TOGGLE BIT
DATA POLLING
3872 FHD F09
DATA Polling (I/O7)
The XM28C020 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a simple
bit test operation to determine the status of the
XM28C020, eliminating additional interrupt inputs or
external hardware. During the internal programming
cycle, any attempt to read the last byte written will
produce the complement of that data on I/O7 (i.e., write
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O7 will reflect true
data. Note: If the XM28C020 is in the protected state and
an illegal write operation is attempted, DATA Polling will
not operate.
Toggle Bit (I/O6)
The XM28C020 also provides another method for deter-
mining when the internal write cycle is complete. During
the internal programming cycle I/O6 will toggle from “1”
to “0” and “0” to “1” on subsequent attempts to read the
last byte written. When the internal cycle is complete the
toggling will cease and the device will be accessible for
additional read or write operations.
3


3Pages


XM28C020P-12 電子部品, 半導体
XM28C020
HARDWARE DATA PROTECTION
The XM28C020 provides three hardware features that
protect nonvolatile data from inadvertent writes.
• Noise Protection—A WE pulse less than 10ns will not
initiate a write cycle.
• Default VCC Sense—All functions are inhibited when
VCC is 3V.
• Write Inhibit—Holding OE LOW will prevent an inad-
vertent write cycle during power-up and power-down.
SOFTWARE DATA PROTECTION
The XM28C020 does provide the Software Data Protec-
tion (SDP) feature.
The module is shipped from Xicor with the Software
Data Protection NOT ENABLED; that is, the module will
be in the standard operating mode. In this mode, data
should be protected during power-up/-down operations
through the use of external circuits. The host system will
then have open read and write access of the module
once VCC is stable.
The module can be automatically protected during power-
up/-down without the need for external circuits by em-
ploying the SDP feature. The internal SDP circuit is
enabled after the first write operation utilizing the SDP
command sequence.
When this feature is employed, it will be easiest to
incorporate in the system software if the module is
viewed as a subsystem composed of four discrete
memory devices with an address decoder (see Func-
tional Diagram). In this manner, system memory map-
ping will extend onto the module. That is, the discrete
memory ICs and decoder should be considered memory
board components and SDP can be implemented at the
component level as described in the next section.
SOFTWARE COMMAND SEQUENCE
A16 and A17 are used by the decoder to select one of the
four LCCs. Therefore, only one of the four memory
devices can be accessed at one time. In order to protect
the entire module, the command sequence must be
issued separately to each device.
Enabling the software data protection mode requires the
host system to issue a series of three write operations:
each write operation must conform to the data and
address sequence illustrated in Figures 6 and 7.
Because this involves writing to a nonvolatile bit, the
device will become protected after tWC has elapsed.
After this point in time devices will inhibit inadvertent
write operations.
Once in the protected mode, authorized writes may be
performed by issuing the same command sequence that
enables SDP, immediately followed by the address/data
combination desired. The command sequence opens
the page write window enabling the host to write from
one to 128 bytes of data. Once the data has been
written, the device will automatically be returned to the
protected state.
In order to facilitate testing of the devices the SDP mode
can be deactivated. This is accomplished by issuing a
series of six write operations: each write operation must
conform to the data and address sequence illustrated in
Figures 8 and 9. This is a nonvolatile operation, and the
host will have to wait a minimum tWC before attempting
to write new data.
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共有リンク

Link :


部品番号部品説明メーカ
XM28C020P-12

5 Volt/ Byte Alterable E2PROM

Xicor Inc.
Xicor Inc.
XM28C020P-15

5 Volt/ Byte Alterable E2PROM

Xicor Inc.
Xicor Inc.


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