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XCV300E-7HQ240C の電気的特性と機能

XCV300E-7HQ240CのメーカーはXilinxです、この部品の機能は「Virtex-E 1.8 V Field Programmable Gate Arrays」です。


製品の詳細 ( Datasheet PDF )

部品番号 XCV300E-7HQ240C
部品説明 Virtex-E 1.8 V Field Programmable Gate Arrays
メーカ Xilinx
ロゴ Xilinx ロゴ 




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XCV300E-7HQ240C Datasheet, XCV300E-7HQ240C PDF,ピン配置, 機能
0
R Virtex™-E 1.8 V
Field Programmable Gate Arrays
DS022-1 (v2.2) November 9, 2001
00
Features
• Fast, High-Density 1.8 V FPGA Family
- Densities from 58 k to 4 M system gates
- 130 MHz internal performance (four LUT levels)
- Designed for low-power operation
- PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz
• Highly Flexible SelectI/O+™ Technology
- Supports 20 high-performance interface standards
- Up to 804 singled-ended I/Os or 344 differential I/O
pairs for an aggregate bandwidth of > 100 Gb/s
• Differential Signalling Support
- LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL
- Differential I/O signals can be input, output, or I/O
- Compatible with standard differential devices
- LVPECL and LVDS clock inputs for 300+ MHz
clocks
• Proprietary High-Performance SelectLink™
Technology
- Double Data Rate (DDR) to Virtex-E link
- Web-based HDL generation methodology
• Sophisticated SelectRAM+™ Memory Hierarchy
- 1 Mb of internal configurable distributed RAM
- Up to 832 Kb of synchronous internal block RAM
- True Dual-Port™ BlockRAM capability
- Memory bandwidth up to 1.66 Tb/s (equivalent
bandwidth of over 100 RAMBUS channels)
- Designed for high-performance Interfaces to
External Memories
- 200 MHz ZBT* SRAMs
- 200 Mb/s DDR SDRAMs
- Supported by free Synthesizable reference design
* ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary Product Specification
• High-Performance Built-In Clock Management Circuitry
- Eight fully digital Delay-Locked Loops (DLLs)
- Digitally-Synthesized 50% duty cycle for Double
Data Rate (DDR) Applications
- Clock Multiply and Divide
- Zero-delay conversion of high-speed LVPECL/LVDS
clocks to any I/O standard
• Flexible Architecture Balances Speed and Density
- Dedicated carry logic for high-speed arithmetic
- Dedicated multiplier support
- Cascade chain for wide-input function
- Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
- Internal 3-state bussing
- IEEE 1149.1 boundary-scan logic
- Die-temperature sensor diode
• Supported by Xilinx Foundation™ and Alliance Series™
Development Systems
- Further compile time reduction of 50%
- Internet Team Design (ITD) tool ideal for
million-plus gate density designs
- Wide selection of PC and workstation platforms
• SRAM-Based In-System Configuration
- Unlimited re-programmability
• Advanced Packaging Options
- 0.8 mm Chip-scale
- 1.0 mm BGA
- 1.27 mm BGA
- HQ/PQ
m• 0.18 m 6-Layer Metal Process
• 100% Factory Tested
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS022-1 (v2.2) November 9, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
1

1 Page





XCV300E-7HQ240C pdf, ピン配列
R Virtex-E 1.8 V Field Programmable Gate Arrays
resources. The abundance of routing resources permits the
Virtex-E family to accommodate even the largest and most
complex designs.
Virtex-E FPGAs are SRAM-based, and are customized by
loading configuration data into internal memory cells. Con-
figuration data can be read from an external SPROM (mas-
ter serial mode), or can be written into the FPGA
(SelectMAP, slave serial, and JTAG modes).
The standard Xilinx Foundation Seriesand Alliance
SeriesDevelopment systems deliver complete design
support for Virtex-E, covering every aspect from behavioral
and schematic entry, through simulation, automatic design
translation and implementation, to the creation and down-
loading of a configuration bit stream.
Higher Performance
Virtex-E devices provide better performance than previous
generations of FPGAs. Designs can achieve synchronous
system clock rates up to 240 MHz including I/O or 622 Mb/s
using Source Synchronous data transmission architech-
tures. Virtex-E I/Os comply fully with 3.3 V PCI specifica-
tions, and interfaces can be implemented that operate at
33 MHz or 66 MHz.
While performance is design-dependent, many designs
operate internally at speeds in excess of 133 MHz and can
achieve over 311 MHz. Table 2 shows performance data for
representative circuits, using worst-case timing parameters.
Table 2: Performance for Common Circuit Functions
Function
Bits Virtex-E (-7)
Register-to-Register
Adder
16 4.3 ns
64 6.3 ns
Pipelined Multiplier
8x8
16 x 16
4.4 ns
5.1 ns
Address Decoder
16
64
3.8 ns
5.5 ns
16:1 Multiplexer
4.6 ns
Parity Tree
9 3.5 ns
18 4.3 ns
36 5.9 ns
Chip-to-Chip
HSTL Class IV
LVTTL,16mA, fast slew
LVDS
LVPECL
Virtex-E Device/Package Combinations and Maximum I/O
Table 3: Virtex-E Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins)
XCV
50E
XCV
100E
XCV
200E
XCV
300E
XCV
400E
XCV XCV XCV XCV XCV
600E 1000E 1600E 2000E 2600E
CS144 94
94
94
PQ240 158
158
158
158
158
HQ240
158 158
BG352
196 260 260
BG432
316 316 316
BG560
404 404 404 404 404
FG256 176
176
176
176
FG456
284 312
FG676
404 444
FG680
512 512 512 512
FG860
660 660 660
FG900
512 660 700
FG1156
660 724 804 804
XCV
3200E
804
DS022-1 (v2.2) November 9, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
3


3Pages





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共有リンク

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部品番号部品説明メーカ
XCV300E-7HQ240C

Virtex-E 1.8 V Field Programmable Gate Arrays

Xilinx
Xilinx
XCV300E-7HQ240I

Virtex-E 1.8 V Field Programmable Gate Arrays

Xilinx
Xilinx


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