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IRF830のメーカーはNXP Semiconductorsです、この部品の機能は「PowerMOS transistor Avalanche energy rated」です。 |
部品番号 | IRF830 |
| |
部品説明 | PowerMOS transistor Avalanche energy rated | ||
メーカ | NXP Semiconductors | ||
ロゴ | |||
このページの下部にプレビューとIRF830ダウンロード(pdfファイル)リンクがあります。 Total 7 pages
Philips Semiconductors
PowerMOS transistor
Avalanche energy rated
Product specification
IRF830
FEATURES
• Repetitive Avalanche Rated
• Fast switching
• High thermal cycling performance
• Low thermal resistance
SYMBOL
g
d
s
QUICK REFERENCE DATA
VDSS = 500 V
ID = 5.9 A
RDS(ON) ≤ 1.5 Ω
GENERAL DESCRIPTION
N-channel, enhancement mode
field-effect power transistor,
intended for use in off-line switched
mode power supplies, T.V. and
computer monitor power supplies,
d.c. to d.c. converters, motor control
circuits and general purpose
switching applications.
The IRF830 is supplied in the
SOT78 (TO220AB) conventional
leaded package.
PINNING
PIN DESCRIPTION
1 gate
2 drain
3 source
tab drain
SOT78 (TO220AB)
tab
1 23
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
ID
IDM
PD
Tj, Tstg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total dissipation
Operating junction and
storage temperature range
Tj = 25 ˚C to 150˚C
Tj = 25 ˚C to 150˚C; RGS = 20 kΩ
Tmb = 25 ˚C; VGS = 10 V
Tmb = 100 ˚C; VGS = 10 V
Tmb = 25 ˚C
Tmb = 25 ˚C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
500
500
± 30
5.9
3.7
24
125
150
UNIT
V
V
V
A
A
A
W
˚C
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
EAS
EAR
IAS, IAR
Non-repetitive avalanche
energy
Unclamped inductive load, IAS = 4.2 A;
tp = 0.21 ms; Tj prior to avalanche = 25˚C;
VDD ≤ 50 V; RGS = 50 Ω; VGS = 10 V; refer
to fig:17
Repetitive avalanche energy1 IAR = 5.9 A; tp = 2.5 µs; Tj prior to
avalanche = 25˚C; RGS = 50 Ω; VGS = 10 V;
refer to fig:18
Repetitive and non-repetitive
avalanche current
MIN.
-
-
-
MAX.
287
10
5.9
UNIT
mJ
mJ
A
1 pulse width and repetition rate limited by Tj max.
March 1999
1
Rev 1.000
1 Page Philips Semiconductors
PowerMOS transistor
Avalanche energy rated
120 PD%
Normalised Power Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Tmb / C
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
ID%
120
Normalised Current Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Tmb / C
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V
ID, Drain current (Amps)
100
10 RDS(ON) = VDS/ID
1
DC
PHP4N50
tp = 10 us
100 us
1 ms
10 ms
0.1
10
100 1000
VDS, Drain-source voltage (Volts)
10000
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Product specification
IRF830
1 Zth j-mb, Transient thermal impedance (K/W) PHP3N60
D = 0.5
0.2
0.1
0.1 0.05
0.02
0.01 single pulse
PD tp
D = tp
T
Tt
0.0011us
10us 100us 1ms
10ms 100ms
tp, pulse width (s)
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
1s
15 ID, Drain current (Amps)
Tj = 25 C
10
PHP4N50
7 V 10 V
6.5 V
6V
5.5 V
5 5V
VGS = 4.5 V
0
0 5 10 15 20 25
VDS, Drain-Source voltage (Volts)
Fig.5. Typical output characteristics.
ID = f(VDS); parameter VGS
30
4 RDS(on), Drain-Source on resistance (Ohms)
4.5 V 5 V 5.5 V
VGS = 6 V
PHP4N50
Tj = 25 C
3
6.5 V 7 V 10 V
2
1
0
0 5 10
ID, Drain current (Amps)
Fig.6. Typical on-state resistance.
RDS(ON) = f(ID); parameter VGS
15
March 1999
3
Rev 1.000
3Pages Philips Semiconductors
PowerMOS transistor
Avalanche energy rated
MECHANICAL DATA
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220
Product specification
IRF830
SOT78
D1
D
E
P
q
L2(1)
b1
L
L1
123
ee
b
A
A1
Q
c
0 5 10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT A A1 b b1 c
D D1 E
eL
mm
4.5 1.39 0.9
4.1 1.27 0.7
1.3
1.0
0.7
0.4
15.8
15.2
6.4
5.9
10.3
9.7
2.54
15.0
13.5
Note
1. Terminals in this zone are not tinned.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
EIAJ
SOT78
TO-220
L1
3.30
2.79
L2(1)
max.
3.0
Pq Q
3.8 3.0 2.6
3.6 2.7 2.2
EUROPEAN
PROJECTION
ISSUE DATE
97-06-11
Fig.19. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g)
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to mounting instructions for SOT78 (TO220AB) package.
3. Epoxy meets UL94 V0 at 1/8".
March 1999
6
Rev 1.000
6 Page | |||
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