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IR21814S の電気的特性と機能

IR21814SのメーカーはInternational Rectifierです、この部品の機能は「HIGH AND LOW SIDE DRIVER」です。


製品の詳細 ( Datasheet PDF )

部品番号 IR21814S
部品説明 HIGH AND LOW SIDE DRIVER
メーカ International Rectifier
ロゴ International Rectifier ロゴ 




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IR21814S Datasheet, IR21814S PDF,ピン配置, 機能
Data Sheet No. PD60172 Rev.G
IR2181(4)(S) &(PbF)
HIGH AND LOW SIDE DRIVER
Features
Floating channel designed for bootstrap operation
Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune
Gate drive supply range from 10 to 20V
Undervoltage lockout for both channels
3.3V and 5V input logic compatible
Matched propagation delay for both channels
Logic and power ground +/- 5V offset.
Lower di/dt gate driver for better noise immunity
Output source/sink current capability 1.4A/1.8A
Also available LEAD-FREE (PbF)
Packages
8-Lead PDIP
IR2181
8-Lead SOIC
IR2181S
14-Lead PDIP
IR21814
14-Lead SOIC
IR21814S
IR2181/IR2183/IR2184 Feature Comparison
Description
The IR2181(4)(S) are high voltage,
high speed power MOSFET and IGBT
drivers with independent high and low
side referenced output channels. Pro-
prietary HVIC and latch immune
CMOS technologies enable rugge-
Part
2181
21814
2183
21834
2184
21844
Input
logic
HIN/LIN
HIN/LIN
IN/SD
Cross-
conduction
prevention
logic
no
yes
yes
Dead-Time
Ground Pins
none
Internal 500ns
Program 0.4 ~ 5 us
Internal 500ns
Program 0.4 ~ 5 us
COM
VSS/COM
COM
VSS/COM
COM
VSS/COM
Ton/Toff
180/220 ns
180/220 ns
680/270 ns
dized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to
3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-
conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side
configuration which operates up to 600 volts.
Typical Connection
VCC
V CC
VB
HIN HIN HO
LIN LIN VS
COM
LO
IR2181
(Refer to Lead Assignments for correct pin
configuration). This/These diagram(s) show
electrical connections only. Please refer to
our Application Notes and DesignTips for
proper circuit board layout.
up to 600V
TO
LOAD
HO
VCC
VCC
VB
HIN HIN VS
LIN LIN
VSS VSS COM
LO
IR21814
up to 600V
TO
LOAD
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IR21814S pdf, ピン配列
IR2181(4) (S) & (PbF)
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15V, VSS = COM, CL = 1000 pF, TA = 25°C.
Symbol
ton
toff
MT
tr
tf
Definition
Turn-on propagation delay
Turn-off propagation delay
Delay matching, HS & LS turn-on/off
Turn-on rise time
Turn-off fall time
Min.
Typ.
180
220
0
40
20
Max. Units Test Conditions
270 VS = 0V
330 VS = 0V or 600V
35 nsec
60
VS = 0V
35 VS = 0V
Static Electrical Characteristics
VBIAS (VCC, VBS) = 15V, VSS = COM and TA = 25°C unless otherwise specified. The VIL, VIH and IIN parameters are
referenced to VSS/COM and are applicable to the respective input leads HIN and LIN. The VO, IO and Ron parameters are
referenced to COM and are applicable to the respective output leads: HO and LO.
Symbol
VIH
VIL
VOH
VOL
ILK
IQBS
IQCC
IIN+
IIN-
VCCUV+
VBSUV+
VCCUV-
VBSUV-
VCCUVH
VBSUVH
IO+
Definition
Logic “1” input voltage (IR2181/IR21814 )
Logic “0” input voltage (IR2181/IR21814)
High level output voltage, VBIAS - VO
Low level output voltage, VO
Offset supply leakage current
Quiescent VBS supply current
Quiescent VCC supply current
Logic “1” input bias current
Logic “0” input bias current
VCC and VBS supply undervoltage positive going
threshold
VCC and VBS supply undervoltage negative going
threshold
Hysteresis
Output high short circuit pulsed current
IO- Output low short circuit pulsed current
Min.
2.7
20
50
8.0
Typ. Max. Units Test Conditions
——
— 0.8
— 1.2
— 0.1
V
VCC = 10V to 20V
VCC = 10V to 20V
IO = 0A
IO = 0A
— 50
60 150
120 240
25 60
— 1.0
8.9 9.8
µA
VB = VS = 600V
VIN = 0V or 5V
VIN = 0V or 5V
VIN = 5V
VIN = 0V
7.4 8.2 9.0 V
0.3 0.7 —
1.4 1.9 —
1.8 2.3 —
A
VO = 0V,
PW 10 µs
VO = 15V,
PW 10 µs
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3Pages


IR21814S 電子部品, 半導体
IR2181(4) (S) & (PbF)
HIN
LIN
HO
LO
Figure 1. Input/Output Timing Diagram
HIN
LIN
ton
HO
LO
50%
50%
tr
90%
toff tf
90%
10%
10%
Figure 2. Switching Time Waveform Definitions
HIN 50%
LIN
50%
LO HO
10%
MT MT
90%
LO HO
Figure 3. Delay Matching Waveform Definitions
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共有リンク

Link :


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