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PDF IR2125 Data sheet ( Hoja de datos )
| Número de pieza | IR2125 | |
| Descripción | CURRENT LIMITING SINGLE CHANNEL DRIVER | |
| Fabricantes | International Rectifier | |
| Logotipo |  |
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Data Sheet No. PD-6.017D
IR2125
CURRENT LIMITING SINGLE CHANNEL DRIVER
Features
n Floating channel designed for bootstrap operation
Fully operational to +500V
Tolerant to negative transient voltage
dV/dt immune
n Gate drive supply range from 12 to 18V
n Undervoltage lockout
n Current detection and limiting loop to limit driven
power transistor current
n Error lead indicates fault conditions and programs
shutdown time
n Output in phase with input
Product Summary
VOFFSET
500V max.
IO+/-
1A / 2A
VOUT
12 - 18V
VCSth
230 mV
ton/off (typ.) 150 & 150 ns
Description
The IR2125 is a high voltage, high speed power
MOSFET and IGBT driver with over-current limit-
ing protection circuitry. Proprietary HVIC and latch
immune CMOS technologies enable ruggedized
monolithic construction. Logic inputs are compat-
ible with standard CMOS or LSTTL outputs. The
output driver features a high pulse current buffer
stage designed for minimum driver cross-conduc-
tion. The protection circuitry detects over-current
in the driven power transistor and limits the gate
drive voltage. Cycle by cycle shutdown is pro-
grammed by an external capacitor which directly
controls the time interval between detection of the
over-current limiting conditions and latched shut-
Package
down. The floating channel can be used to drive an
N-channel power MOSFET or IGBT in the high or
low side configuration which operates up to 500
volts.
Typical Connection
up to 500V
VCC
VCC
VB
IN IN OUT
ERR
CS
COM
VS
TO
LOAD
To Order
CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-107
1 page  
Previous Datasheet
Device Information
Process & Design Rule
Transistor Count
Die Size
Die Outline
Index
Next Data Sheet
IR2125
HVDCMOS 4.0 µm
410
104 X 111 X 26 (mil)
Thickness of Gate Oxide
Connections
Material
First Width
Layer
Spacing
Thickness
Material
Second
Width
Layer
Spacing
Thickness
Contact Hole Dimension
Insulation Layer
Material
Thickness
Passivation
Material
(1) Thickness
Passivation
Material
(2) Thickness
Method of Saw
Method of Die Bond
Wire Bond
Method
Material
Leadframe
Material
Die Area
Lead Plating
Package
Types
Materials
Remarks: * Patent Pending
800Å
Poly Silicon
4 µm
6 µm
5000Å
Al - Si (Si: 1.0% ±0.1%)
6 µm
9 µm
20,000Å
8 µm X 8 µm
PSG (SiO2)
1.5 µm
PSG (SiO2)
1.5 µm
Proprietary*
Proprietary*
Full Cut
Ablebond 84 - 1
Thermo Sonic
Au (1.0 mil / 1.3 mil)
Cu
Ag
Pb : Sn (37 : 63)
8 Lead PDIP
EME6300 / MP150 / MP190
To Order
CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-111
5 Page 
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Index
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IR2125
1.0 0
0.8 0
0.6 0
0.4 0
0.2 0
Max.
0.0 0
-50
-25
0 25 50 75
Temperature (°C)
100 125
Figure 19A. Low Level Output vs. Temperature
1.0 0
0.8 0
0.6 0
0.4 0
0.2 0
Max.
0.0 0
10 12 14 16 18
VBS Floating Supply Voltage (V)
Figure 19B. Low Level Output vs. Voltage
20
500
400
300
200
100
Max.
0
-50 -25 0 25 50 75 100 125
Temperature (°C)
Figure 20A. Offset Supply Current vs. Temperature
500
400
300
200
100
Max.
0
0 100 200 300 400 500
VB Boost Voltage (V)
Figure 20B. Offset Supply Current vs. Voltage
2.0 0
2.0 0
1.6 0
1.6 0
1.2 0
Max.
0.8 0
1.2 0
0.80 Max.
0.4 0
Typ.
0.4 0
Typ.
0.0 0
-50
-25
0 25 50 75
Temperature (°C)
100 125
Figure 21A. VBS Supply Current vs. Temperature
0.0 0
10
12 14 16 18
VBS Floating Supply Voltage (V)
Figure 21B. VBS Supply Current vs. Voltage
20
To Order
CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-117
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet IR2125.PDF ] | |
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