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PDF SAA7205H Data sheet ( Hoja de datos )
| Número de pieza | SAA7205H | |
| Descripción | MPEG-2 systems demultiplexer | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
SAA7205H
MPEG-2 systems demultiplexer
Preliminary specification
File under Integrated Circuits, IC02
1997 Jan 21
1 page  
Philips Semiconductors
MPEG-2 systems demultiplexer
5 BLOCK DIAGRAM
Preliminary specification
SAA7205H
handbook, full pagewidth
1997 Jan 21
5
5 Page 
Philips Semiconductors
MPEG-2 systems demultiplexer
Preliminary specification
SAA7205H
7 FUNCTIONAL DESCRIPTION
7.1 Functional overview
A schematic diagram of the internal structure of the
MPEG-2 demultiplexer is shown in Fig.2. The diagram
illustrates the main functional entities in the demultiplexer.
7.1.1 MPEG-2 SYNTAX PARSER
The MPEG-2 syntax parser, parsing transport streams
which comply with the MPEG-2 systems specification
(International Standard, November 1994).
7.1.2 ERROR HANDLING
Error handling is invoked whenever an error is detected.
Error handling is started on the basis of either the
PKTBAD/PKTBAD input signal (driven by the FEC
decoder), or the transport_error_indicator in the transport
packet header, or discovery of a syntax error by the parser.
7.1.3 TELETEXT FILTER
A teletext (TXT) filter, generating a teletext clock
(TTC = 6.75 MHz, derived from the chip clock,
CCLKI = 27 MHz) and providing a serial TXT data stream
(TTD) locked to both TTC and the horizontal video sync
(HSYNC) generated by the demultiplexer. In accordance
with the DVB specification, TXT data is transported in
MPEG-2 PES packets. The incoming transport stream is
filtered on the basis of a Programmable Packet
Identification (PID) and elementary stream data is stored
in a 2 kbyte FIFO buffer. Data is read from the TXT buffer
at 6.75 Mbit/s.
The TXT filter can, alternatively, be programmed to a
mode in which it provides TXT bits at 6.9375 MHz, on the
basis of an external request (TTR). This mode is applied
for vertical blanking interval insertion of TXT data. It is
compatible with the TXT input of the EURO-DENC
(SAA7183).
7.1.4 GENERIC DATA FILTER
A generic data filter is connected to the generic interface.
This filter in fact does not filter, but passes the entire
transport stream in byte format. A byte strobe signal
(GPST), indicating consecutive valid bytes, a valid signal
(GPV) and a header sync byte indicator (GPSYNC) are
generated.
Alternatively the general purpose interface can be
configured to function as transport stream input
(GP_Direction = 1; address 0x0700; see Table 13).
7.1.5 HIGH SPEED DATA FILTER
A high speed data filter (HS), retrieves the entire transport
packets, packet payloads, PES payloads or sections from
the input stream on the basis of a programmable filter.
Data is output at the byte clock frequency
(DCLK = 9 MHz = CCLKI/3, 33% duty cycle). Selected
parts of a data stream are indicated by the HSV signal.
The first byte of a data entity is indicated by HSSYNC. The
HS filter shares its data output pins with the generic data
filter.
It should be noted that in the event that the HS filter is
programmed to the section mode, the GP bus only outputs
selected sections and not an entire transport stream.
7.1.6 VIDEO DATA FILTER
A video data filter, with a decoder specific interface. This
filter selects either Packetized Elementary Stream (PES)
data, or Elementary Stream (ES) data (programmable) on
the basis of a programmable PID, and passes it to the
video FIFO. Presentation Time Stamps and Decoding
Time Stamps (PTS and DTS) are obtained from the PES
stream and can be read by the microcontroller (optional).
Video PES or ES data is output at 9 MHz, via a
bidirectional 8-bit wide bus which is time-shared with the
microcontroller. Access to the output bus is controlled by
the microcontroller using the VSEL signal.
The demultiplexer therefore, halts output video data
whenever VSEL = 0 and creates a bidirectional
communication link between the microcontroller and the
video decoder.
7.1.7 AUDIO DATA FILTER
An audio data filter with a decoder specific interface. This
filter selects PES or ES data (programmable) on the basis
of a programmable PID and passes it to the audio FIFO.
Time-stamps are retrieved from audio PES headers and
can be read by the microcontroller (optional).
The audio filter can be switched to a mode in which the
microcontroller controls audio and video synchronization
(software sync). In this mode the filter outputs audio data
at 9 Mbit/s. The filter is also capable of handling
synchronization independently from the microcontroller.
In this situation the audio elementary stream output is
(hardware) synchronized to the System Time Clock (STC)
automatically. In the hardware synchronization mode, the
audio elementary stream data is output via a bit serial data
link at a bit rate between 32 to 448 kbit/s. The actual bit
rate depends on the type of audio frame that is handled
(as specified in the MPEG-2 audio specification).
1997 Jan 21
11
11 Page | ||
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| PDF Descargar | [ Datasheet SAA7205H.PDF ] | |
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