DataSheet.jp

SC26L198A1A の電気的特性と機能

SC26L198A1AのメーカーはNXP Semiconductorsです、この部品の機能は「Octal UART with TTL compatibility at 3.3V and 5V supply voltages」です。


製品の詳細 ( Datasheet PDF )

部品番号 SC26L198A1A
部品説明 Octal UART with TTL compatibility at 3.3V and 5V supply voltages
メーカ NXP Semiconductors
ロゴ NXP Semiconductors ロゴ 




このページの下部にプレビューとSC26L198A1Aダウンロード(pdfファイル)リンクがあります。
Total 30 pages

No Preview Available !

SC26L198A1A Datasheet, SC26L198A1A PDF,ピン配置, 機能
Philips Semiconductors
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
Product specification
SC26C198 SC68C198
SC26L198 SC68L198
Table of Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Uses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . 338
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 339
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Functional Description . . . . . . . . . . . . . . . . . . . . . 340
Conceptual Overview . . . . . . . . . . . . . . . . . . . . . . . 340
Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Asynchronous bus cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Synchronous bus cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Timing Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Sclk – System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Baud Rate Generator BRG . . . . . . . . . . . . . . . . . . . . . . . . 341
BRG Counters (Used for random baud rate generation) 341
Channel Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Character Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Detailed Descriptions . . . . . . . . . . . . . . . . . . . . . . . 342
Receiver and Transmitter . . . . . . . . . . . . . . . . . . . 342
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Transmitter Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Transmission of ”break” . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
1x and 16x modes, Transmitter . . . . . . . . . . . . . . . . . . . . . 343
Transmitter FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
1x and 16x mode, Receiver . . . . . . . . . . . . . . . . . . . . . . . . . 343
Receiver Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Receiver FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
RxFIFO Status: Status reporting modes . . . . . . . . . . . . . . 344
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
General Purpose Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Character Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Xon Xoff Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Multi-drop or Wake up or 9 bit mode . . . . . . . . . . . . . . . . . 345
Character Stripping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Interrupt Arbitration and IRQN generation . . . . . . . . . . . . . . . . 345
IACKN Cycle, Update CIR . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Enabling and Activating Interrupt sources . . . . . . . . . . . . . 346
Setting Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . 347
Major Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Minor Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Watch-dog Timer Time–out Mode . . . . . . . . . . . . . . . . . . . 348
Wake Up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Xon/Xoff Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
REGISTER DEfiniTIONS . . . . . . . . . . . . . . . . . . . . 351
MR – Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
UCIR – Update CIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
General Purpose Output Pin Control . . . . . . . . 361
Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Register Map Summary . . . . . . . . . . . . . . . . . . . . . 363
Register Map Detail . . . . . . . . . . . . . . . . . . . . . . . . 364
Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Device Configuration after Hardware Reset or CRa cmd=x1F 372
Cleared registers: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Clears Modes for: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Disables: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Halts: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Limitations: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
DC Electrical Specifications
(26C198 and 68C198) . . . . . . . . . . . . . . . . . . . . . . . 373
DC Electrical Specifications
(26L198 and 68L198) . . . . . . . . . . . . . . . . . . . . . . . 376
AC Electrical Characteristics5 (26L198 and
68L198) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
DESCRIPTION
The Philips 26C198 Octal UART is a single chip CMOS–LSI
communications device that provides 8 full-duplex asynchronous
channels with significantly deeper 16 byte FIFOs, Automatic
in–band flow control using Xon/Xoff characters defined by the user
and address recognition in the wake up mode. Synchronous bus
interface is used for all communication between host and OCTART.
It is fabricated using Philips 1.0 micron CMOS technology that
combines the benefits of low cost, high density and low power
consumption.
The operating speed of each receiver and transmitter can be
selected independently from one of 22 fixed baud rates, a 16X clock
derived from one of two programmable baud rate counters or one of
three external 16X clocks (1 available at 1x clock rate). The baud
rate generator and counter can operate directly from a crystal or
from seven other external or internal clock inputs. The ability to
independently program the operating speed of the receiver and
transmitter makes the Octal UART particularly attractive for dual
speed full duplex channel applications such as clustered terminal
systems. The receivers and transmitters are buffered with FIFOs of
16 characters to minimize the potential for receiver overrun and to
reduce interrupt overhead. In addition, a handshaking capability and
in–band flow control are provided to disable a remote UART
transmitter when the receiver buffer is full or nearly so.
To minimize interrupt overhead an interrupt arbitration system is
included which reports the context of the interrupting UART via
direct access or through the modification of the interrupt vector. The
context of the interrupt is reported as channel number, type of
device interrupting ( receiver COS etc.) and, for transmitters or
receivers, the fill level of the FIFO.
The Octal UART provides a power down mode in which the
oscillator is stopped but the register contents are maintained. This
results in reduced power consumption of several orders of
magnitudes. The Octal UART is fully TTL compatible when
operating from a single +5V power supply. Operation at 3.3 volts is
maintained with CMOS interface levels.
The device also offered in a version which maintains TTL input and
output levels while operating with a 3.3 volt power supply.
1995 May 1
336 853-1756 15179

1 Page





SC26L198A1A pdf, ピン配列
Philips Semiconductors
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
Product specification
SC26C198 SC68C198
SC26L198 SC68L198
PIN CONFIGURATIONS
11
12
1 75
74
84-Pin PLCC
TOP VIEW
32 54
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁPINÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁOUÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁTP1111111112222222221123456789ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁi1023456789012345678n ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁFDuWRRRIIIIIIIIITTIIIITÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁCA/////////V////nVVOOOOOOOOOOOOOAAAxxxxx_xCEcCSsDDDDDDR2100123012300123tsCSNKiabcaaaabbbbdabcccccNÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁoNn ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁP2333333333344444444445555555ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁi9012345678901234567890123456n 33ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁFRu5GERRIIIIIIIITTÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁGG3////////VnVVVOOOOOOOODDDDDDDDSxxoxxiicCSssDDnnDDuE0123456712332103tssCS01tidhdddhhhhgdhTÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ0oNn ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁP5556666666666777777777788888ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁi7890123456789012345678901234n ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁFIuSRRIAIIIIIIIÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁTTRIIIITR///////nV////OOOOOOOCXXAAAAAxxCxxOOOOxxcQSDDDDD1276543LD2103210K3210tSNigeKgggeeeegeÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁfNfffffon ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
1995 May 1
338


3Pages


SC26L198A1A 電子部品, 半導体
Philips Semiconductors
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
Product specification
SC26C198 SC68C198
SC26L198 SC68L198
Timing Circuits
The timing block consists of a crystal oscillator, a fixed baud rate
generator (BRG), a pair of programmable 16 bit register based
counters. A buffer for the System Clock generates internal timing for
processes not directly concerned with serial data flow.
Crystal Oscillator
The crystal oscillator operates directly from a crystal, tuned between
1.0 and 8.0 MHz, connected across the X1/CCLK and X2 inputs with
a minimum of external components. BRG values listed for the clock
select registers correspond to a 3.6864 MHz crystal frequency. Use
of a 7.3728 MHz crystal will double the Communication Clock
frequencies.
An external clock in the 100 KHz to 10 MHz frequency range may
be connected to X1/CCLK. If an external clock is used instead of a
crystal, X1/CCLK must be driven and X2 left floating. The X1 clock
serves as the basic timing reference for the baud rate generator
(BRG) and is available to the BRG timers . The X1 oscillator input
may be left unused if the internal BRG is not used and the X1 signal
is not selected for any counter input.
Sclk – System Clock
A clock frequency, within the limits specified in the electrical
specifications, must be supplied for the system clock Sclk. To
ensure the proper operation of internal controllers, the Sclk
frequency provided, must be strictly greater than twice the frequency
of X1 crystal clock, or any external 1x data clock input. The system
clock serves as the basic timing reference for the host interface and
other internal circuits.
Baud Rate Generator BRG
The baud rate generator operates from the oscillator or external
X1/CCLK clock input and is capable of generating 22 commonly
used data communications baud rates ranging from 50 to 230.4K
baud. These common rates may be doubled (up to 460.8 and 500K
baud) when faster clocks are used on the X1/X2 clock inputs. (See
Receiver and Transmitter Clock Select Register descriptions.) All of
these are available simultaneously for use by any receiver or
transmitter. The clock outputs from the BRG are at 16X the actual
baud rate.
BRG Counters (Used for random baud rate generation)
The two BRG Timers are programmable 16 bit dividers that are used
for generating miscellaneous clocks. These clocks may be used by
any or all of the receivers and transmitters in the Octart or output on
the general purpose output pin GPO.
Each timer unit has eight different clock sources available to it as
described in the BRG Timer Control Register. (BRGTCR). Note
that the timer run and stop controls are also contained in this
register. The BRG Timers generate a symmetrical square wave
whose half period is equal in time to the division of the selected
BRG Timer clock source by the number loaded to the BRG Timer
Reload Registers ( BRGTRU and BRGTRL). Thus, the output
frequency will be the clock source frequency divided by twice the
value loaded to the BRGTRU and BRGTRL registers. This is the
result of counting down once for the high portion of the output wave
and once for the low portion.
Whenever the these timers are selected via the receiver or
transmitter Clock Select register their output will be configured as a
16x clock for the respective receiver or transmitter. Therefore one
needs to program the timers to generate a clock 16 times faster than
the data rate. The formula for calculating ’n’, the number loaded to
the BRGTRU and BRGTRL registers, is shown below.
ǒ Ǔn +
BRG Timer Input frequency
2 @ 16 @ desired baud rate
–1
Note: ’n’ may assume values of 0 and 1. In previous Philips data
communications controllers these values were not allowed.
The BRG timer input frequency is controlled by the BRG Timer
control register (BRGTCR)
The frequency generated from the above formula will be at a rate 16
times faster than the desired baud rate. The transmitter and
receiver state machines include divide by 16 circuits which provide
the final frequency and provide various timing edges used in the
qualifying the serial data bit stream. Often this division will result in
a non–integer value; 26.3 for example. One may only program
integer numbers to a digital divider. There for 26 would be chosen.
If 26.7 was the result of the division then 27 would be chosen. This
gives a baud rate error of 0.3/26.3 or 0.3/26.7. which yields a
percentage error of 1.14% or 1.12% respectively; well within the
ability of the asynchronous mode of operation.
One should be cautious about the assumed benign effects of small
errors since the other receiver or transmitter with which one is
communicating may also have a small error in the precise baud rate.
In a ”clean” communications environment using one start bit, eight
data bits and one stop bit the total difference allowed between the
transmitter and receiver frequency is approximately 4.6%. Less
than eight data bits will increase this percentage.
Channel Blocks
There are eight channel blocks, each containing an I/O port control,
a data format control, and a single full duplex UART channel
consisting of a receiver and a transmitter with their associated 16
byte FIFOs. Each block has its own status register, interrupt status
and interrupt mask registers and their interface to the interrupt
arbitration system.
A highly programmable character recognition system is also
included in each block. This system is used for the Xon/Xoff flow
control and the multi-drop (”9 bit mode”) address character
recognition. It may also be used for general purpose character
recognition.
Four I/O pins are provided for each channel. These pins are
configured individually to be inputs or outputs. As inputs they may
be used to bring external data to the bus, as clocks for internal
functions or external control signals. Each I/O pin has a ”Change of
State” detector. The change detectors are used to signal a change
in the signal level at the pin (Either 0 to 1 or 1 to 0). The level
change on these pins must be stable for 25 to 50 Us (two edges of
the 38.4 KHz baud rate clock) before the detectors will signal a valid
change. These are typically used for interface signals from modems
to the OCTART and from there to the host. See the description of
the ”UART channel” under detailed descriptions below.
Character Recognition
Character recognition is specific to each of the eight UARTs. Three
programmable characters are provided for the character recognition
for each channel. The three are general purpose in nature and may
be set to only cause an interrupt or to initiate some rather complex
operations specific to ”Multi-drop” address recognition or in–band
Xon/Xoff flow control.
Character recognition is accomplished via CAM memory. The
Content Addressable Memory continually examines the incoming
data stream. Upon the recognition of a control character appropriate
bits are set in the Xon/Xoff Interrupt Status Register (XISR) and
Interrupt Status Register (ISR). The setting of these bit(s) will
1995 May 1
341

6 Page



ページ 合計 : 30 ページ
 
PDF
ダウンロード
[ SC26L198A1A データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
SC26L198A1A

Octal UART with TTL compatibility at 3.3V and 5V supply voltages

NXP Semiconductors
NXP Semiconductors


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap