DataSheet.jp

SC26C562A8AのメーカーはNXP Semiconductorsです、この部品の機能は「CMOS dual universal serial communications controller CDUSCC」です。 このページではSC26C562A8Aの詳細な仕様と技術情報(パラメータ、電気的特性、ピン配置など)を見つけることができます.


SC26C562A8A の電気的特性と機能

部品番号 SC26C562A8A
部品説明 CMOS dual universal serial communications controller CDUSCC
メーカ NXP Semiconductors
ロゴ NXP Semiconductors ロゴ 




このページの下部にプレビューとSC26C562A8Aダウンロード(pdfファイル)リンクがあります。

Total 22 pages

No Preview Available !

SC26C562A8A Datasheet, SC26C562A8A PDF,ピン配置, 機能
INTEGRATED CIRCUITS
SC26C562
CMOS dual universal serial
communications controller (CDUSCC)
Product specification
Supersedes data of 1995 May 01
IC19 Data Handbook
1998 Sep 04
Philips
Semiconductors

1 Page





SC26C562A8A pdf, ピン配列
Philips Semiconductors
CMOS dual universal serial communications controller
(CDUSCC)
Product specification
SC26C562
Odd or even parity, no parity, or force parity
Up to two stop bits programmable in 1/16-bit increments
1X or 16X Rx and Tx clock factors
Parity, overrun and framing error detection
False start bit detection
Break generation with handshake for counting break characters
Detection of start and end of received break
Character compare with optional interrupt on match
Transmit and receive up to 10Mbps at 1x or 1Mbps at 16x data
rates
Bit-Oriented Protocol
Character length: 5 to 8 bits
Detection and transmission of residual character: 0–7 bits
Automatic switch to programmed character length for I field
Zero insertion and deletion
Optional opening PAD transmission
Detection and generation of FLAG, ABORT, and IDLE bit patterns
Transmit 7 or 8 bit ABORT
Detection and generation of shared (single) FLAG between
frames
Detection of overlapping (shared zero) FLAGs
Idle in MARK or FLAGs
Secondary address recognition including group and global
address
Single- or dual-octet secondary address
Extended address and control fields
Short frame rejection for receiver
Detection and notification of received end of message
CRC generation and checking
SDLC loop mode capability
Character-Oriented Protocols
Character length: 5 to 8 bits
Odd or even parity, no parity, or force parity
LRC or CRC generation and checking
Optional opening PAD transmission
One or two SYN characters
External sync capability
SYN detection and optional stripping
SYN or MARK line-fill or underrun
Idle in MARK or SYNs
Parity, FCS, overrun and underrun error detection
Optional SYNC exclusion from FCS
BISYNC features
EBCDIC or ASCII header, text and control messages
SYN, DLE stripping
EOM (end of message) detection and transmission
Auto transparency mode switching
Auto hunt after receipt of EOM sequence (with closing PAD
check after EOT or NAK)
Control character sequence detection for both transparent and
normal text
Parity generation for data and LRC characters
ORDERING INFORMATION
DESCRIPTION
48-Pin Plastic Dual In-Line Package (DIP)
52-Pin Plastic Leaded Chip Carrier (PLCC) Package
COMMERCIAL
Serial Data Rate =
10Mbps Maximum
SC26C562C1N
SC26C562C1A
INDUSTRIAL
Serial Data Rate =
8Mbps Maximum
Not available
SC26C562A8A
DWG #
SOT240-1
SOT238-3
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
TA
TSTG
VCC
VS
PARAMETER
Operating ambient temperature2
Storage temperature
Voltage from VCC to GND3
Voltage from any pin to ground3
COMMERCIAL
0 to +70
-65 to +150
–0.5 to +7.0
–0.5 to VCC +0.5
RATING
INDUSTRIAL
-40 to +85
-65 to +150
–0.5 to +7.0
–0.5 to VCC +0.5
UNIT
°C
°C
V
V
1998 Sep 04
3


3Pages


SC26C562A8A 電子部品, 半導体
Philips Semiconductors
CMOS dual universal serial communications controller
(CDUSCC)
Product specification
SC26C562
PIN DESCRIPTION
MNEMONIC
PIN NO.
DIP PLCC
A1–A6
D0–D7
4-2,
47-45
31-28,
21-18
4-2,
51-49
33-30,
23-20
RDN
22 24
WRN
26 28
CSN
25 27
RDYN
78
IRQN
IACKN
X1/CLK
66
11
43 47
X2
RESETN
RxDA, RxDB
TxDA, TxDB
42 46
23 25
37, 12 40, 14
36, 13 39, 15
RTxCA, RTxCB 39, 10 43, 11
TRxCA, TRxCB
40, 9 44, 10
TYPE
NAME AND FUNCTION
I Address Lines: Active-high. Address inputs which specify which of the internal registers
is accessed for read/write operation.
I/O Bidirectional Data Bus: Active-high, 3-State. Bit 0 is the LSB and bit 7 is the MSB. All
data, command and status transfers between the CPU and the CDUSCC take place over
this bus. The data bus is enabled when CSN and RDN, or CSN and WRRN are low during
interrupt acknowledge cycles and single address DMA acknowledge cycles.
I Read Strobe: Active-low input. When active and CSN is also active, causes the content
of the addressed register to be present on the data bus. RDN is ignored unless CSN is
active.
I Write Strobe: Active-low input. When active and CSN is also active, the content of the
data bus is loaded into the addressed register. The transfer occurs on the rising edge of
WRN. WRN is ignored unless CEN is active.
I Chip Select: Active-low input. When active, data transfers between the CPU and the
CDUSCC are enabled on D0–D7 as controlled by RDN or WRN and A1–A6 inputs. When
CSN is high, the data lines are placed in the 3-State condition (except during interrupt
acknowledge cycles and single address DMA transfers).
O Ready: Active-low, open drain. Used to synchronize data transfers between the CPU and
the CDUSCC. It is valid only during read and write cycles where the CDUSCC is
configured in ‘wait on Rx’, ‘wait on Tx’ or ‘wait on Tx or Rx’ modes, otherwise it is always
inactive. RDYN becomes active on the leading edge of RDN and WRN if the requested
operation cannot be performed (viz, no data in RxFIFO in the case of a read or no room in
the TxFIFO in the case of a write).
O Interrupt Request: Active-low, open-drain. This output is asserted upon occurrence of
any enabled interrupting condition. The CPU can read the general status register to
determine the interrupting condition(s), or can respond with an interrupt acknowledge cycle
to cause the CDUSCC to output an interrupt vector on the data bus.
I Interrupt Acknowledge: Active-low. When IACKN is asserted, the CDUSCC responds
by either forcing the bus into high-impedance, placing a vector number, call instruction or
zero on the data bus. The vector number can be modified or unmodified by the status. If
no interrupt is pending, IACKN is ignored and the data bus placed in high-impedance.
I Crystal or External Clock: When using the crystal oscillator, the crystal is connected
between pins X1 and X2. If a crystal is not used, an external clock is supplied at this input.
This clock is used to drive the internal bit rate generator, as an optional input to the
counter/timer or DPLL, and to provide other required clocking signals. When a crystal is
used, a capacitor must be connected from this pin to ground.
O Crystal 2: Connection for other side of crystal. When a crystal is used, a capacitor must
be connected from this pin to ground. If an external clock is used on X1, this pin should be
left floating.
I Master Reset: Active-low. A low on this pin resets the transmitters and receivers and
resets the registers shown in Table 1 of the CDUSCC Users’ Guide. Reset is
asynchronous, i.e., no clock is required.
I Channel A (B) Receiver Serial Data Input: The least significant bit is received first. If
external receiver clock is specified for the channel, the input is sampled on the rising edge
of the clock.
O Channel A (B) Transmitter Serial Data Output: The least significant bit is transmitted
first. This output is in the marking (high) condition when the transmitter is disabled or when
the channel is operating in local loopback mode. If external transmitter clock is specified
for the channel, the data is shifted on the falling edge of the clock.
I/O Channel A (B) Receiver/Transmitter Clock: As an input, it can be programmed to
supply the receiver, transmitter, counter/timer, or DPLL clock. As an output, it can supply
the counter/timer output, the transmitter shift clock (1X), or the receiver sampling clock
(1X).
I/O Channel A (B) Transmitter/Receiver Clock: As an input, it can supply the receiver,
transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer
output, the DPLL output, the transmitter shift clock (1X), the receiver sampling clock (1X),
the transmitter BRG clock (16X), The receiver BRG clock (16X), or the internal system
clock (X1 ÷ 2).
1998 Sep 04
6

6 Page



ページ 合計 : 22 ページ
 
PDF
ダウンロード
[ SC26C562A8A datasheet.PDF ]


SC26C562A8A データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 また、SC26C562A8Aのさまざまなアプリケーション回路とユースケースを使用して独自の設計に統合する方法を理解するのに役立ちます。


共有リンク

Link :


おすすめデータシート

あなたの検索基準に基づいて、興味のある他のデータシートを見つけました。同様の部品も一緒に検討することをお勧めします。

部品番号部品説明メーカ
SC26C562A8A

CMOS dual universal serial communications controller CDUSCC

NXP Semiconductors
NXP Semiconductors


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap