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PDF ISL6557 Data sheet ( Hoja de datos )
| Número de pieza | ISL6557 | |
| Descripción | Multi-Phase PWM Controller for Core-Voltage Regulation | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
August 2003
ISL6557
FN9059.2
Multi-Phase PWM Controller for
Core-Voltage Regulation
The ISL6557 provides core-voltage regulation by driving up
to four interleaved synchronous-rectified buck-converter
channels in parallel. Intersil multi-phase controllers together
with Intersil MOSFET drivers form the basis for the most
reliable power-supply solutions available to power the latest
industry-leading microprocessors. Multi-phase buck-
converter architecture uses interleaved timing to multiply
ripple frequency and reduce input and output ripple currents.
Lower ripple results in lower total component cost, reduced
dissipation, and smaller implementation area. Pre-
configured for 4-phase operation, the ISL6557 offers the
flexibility of selectable 2- or 3-phase operation. Simply
connect the unused PWM pins to VCC. The channel
switching frequency is adjustable in the range of 50kHz to
1.5MHz giving the designer the ultimate flexibility in
managing the balance between high-speed response and
good thermal management.
New features on the ISL6557 include Dynamic-VID™
technology allowing seamless on-the-fly VID changes with
no need for any additional external components. When the
ISL6557 receives a new VID code, it incrementally steps the
output voltage to the new level. Dynamic VID changes are
fast and reliable with no output voltage overshoot or
undershoot. The RGND and VSEN pins provide inputs for
differential remote voltage sensing to improve regulation and
protection accuracy. A threshold-sensitive enable pin (EN)
can be used with an external resistor divider to optionally set
the power-on voltage level. This allows optional start-up
coordination with Intersil MOSFET drivers or any other
devices powered from a separate supply.
Like other Intersil multiphase controllers, the ISL6557 uses
cost and space-saving rDS(ON) sensing for channel current
balance, dynamic voltage positioning, and overcurrent
protection. Channel current balancing is automatic and
accurate with the integrated current-balance control system.
Overcurrent protection can be tailored to any application with
no need for additional parts. The IOUT pin carries a signal
proportional to load current and can be optionally connected
to FB for accurate load-line regulation.
An integrated DAC decodes the 5-bit logic signal present at
VID4-VID0 and provides an accurate reference for precision
voltage regulation. The high-bandwidth error amplifier,
differential remote-sensing amplifier, and accurate voltage
reference all work together to provide better than 0.8% total
system accuracy, and to enable the fastest transient
response available.
Features
• Multi-Phase Power Conversion
• Active Channel Current Balancing
• Precision rDS(ON) Current Sensing
- Low Cost
- Lossless
• Precision CORE Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.8% System Accuracy
• Microprocessor Voltage Identification Input
- Dynamic VID technology
- 5-Bit VID Input
- 1.100V to 1.850V in 25mV Steps
• Programmable Power-On Bias Level
• Programmable Droop Voltage
• Fast Transient Recovery Time
• Precision Enable Threshold
• Overcurrent Protection
• 2-, 3-, or 4-Phase Operation
• High Ripple Frequency. Channel Frequency Times
Number Channels (100kHz to 6MHz)
Ordering Information
PART NUMBER TEMP. (oC) PACKAGE PKG. DWG. #
ISL6557CB
0 to 70
24-Ld SOIC M24.3
ISL6557CB-T
24-Ld SOIC Tape and Reel
Pinout
ISL6557 24 PIN (SOIC)
TOP VIEW
VID4 1
VID3 2
VID2 3
VID1 4
VID0 5
COMP 6
FB 7
IOUT 8
VDIFF 9
VSEN 10
RGND 11
GND 12
24 VCC
23 EN
22 FS
21 PGOOD
20 PWM4
19 ISEN4
18 ISEN1
17 PWM1
16 PWM2
15 ISEN2
14 ISEN3
13 PWM3
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners. Dynamic VID™ is a trademark of Intersil Americas Inc.
1 page  
ISL6557
Electrical Specifications Operating Conditions: VCC = 5V, TA = 0oC to 70oC, Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
ISEN
Overcurrent Trip Level
-90 -75 -60
PROTECTION and MONITOR
Overvoltage Threshold
VSEN Rising
2.04 2.09 2.13
VSEN Falling
VID
Undervoltage Threshold
VSEN Rising
0.810
0.990
VSEN Falling
0.835
0.925
PGOOD Low Voltage
IPGOOD = 4mA
0.18 0.4
UNITS
µA
V
V
V
V
mV
NOTES:
2. These parts are designed and adjusted for accuracy within the system tolerance given in the Electrical Specifications. The system tolerance
accounts for offsets in the differential and error amplifiers; reference-voltage inaccuracies; temperature drift; and the full DAC adjustment range.
3. VID input levels above 2.9V may produce an reference-voltage offset inaccuracy.
Functional Pin Descriptions
VID4 1
VID3 2
VID2 3
VID1 4
VID0 5
COMP 6
FB 7
IOUT 8
VDIFF 9
VSEN 10
RGND 11
GND 12
24 VCC
23 EN
22 FS
21 PGOOD
20 PWM4
19 ISEN4
18 ISEN1
17 PWM1
16 PWM2
15 ISEN2
14 ISEN3
13 PWM3
VID4, VID3, VID2, VID1, VID0 (Pins 1, 2, 3, 4, 5)
These are the inputs to the internal DAC that provides the
reference voltage for output regulation. Connect these pins
to either open-drain or active-pull-up type outputs. Pulling
these pins above 2.9V can cause a reference offset
inaccuracy.
FB (Pin 7) and COMP (Pin 6)
The internal error amplifier’s inverting input and output
respectively. These pins are connected to an external R-C
network to compensate the regulator.
IOUT (Pin 8)
The current out of this pin is proportional to output current
and is used for load-line regulation and load sharing. The
scale factor is set by the ratio of the ISEN resistors
(connected to pins 14, 15, 18, and 19) to the lower
MOSFET rDS(ON).
VDIFF (Pin 9), VSEN (Pin 10), RGND (Pin 11)
VSEN and RGND are the inputs to the differential remote-
sense amplifier. VDIFF is the output and it serves as the
input to the external regulation circuitry and the internal
protection circuitry. Connect VSEN and RGND to the sense
pins of the remote load.
GND (Pin 12)
Return for VCC and signal ground for the IC.
PWM3, PWM2, PWM1, PWM4 (Pins 13, 16, 17, 20)
Pulse-width modulation outputs. These logic outputs tell the
driver IC(s) when to turn the MOSFETs on and off.
ISEN3, ISEN2, ISEN1, ISEN4 (PINS 14, 15, 18, 19)
Current sense inputs. A resistor connected between these
pins and the respective phase nodes has a current
proportional to the current in the lower MOSFET during its
conduction interval. The current is used as a reference for
channel balancing, load sharing, protection, and load-line
regulation.
PGOOD (Pin 21)
PGOOD is an open-drain logic output that changes to a logic
low when the differential output voltage at VDIFF swings
below 0.9V or above 2.1V.
FS (Pin 22)
This pin has two functions. A resistor placed from FS to
ground sets the switching frequency. There is an inverse
relationship between the value of the resistor and the
switching frequency. This pin can also be used to disable the
controller. To disable the controller, pull this pin below 1V.
EN (Pin 23)
This is the threshold-sensitive enable input for the controller.
To enable the controller, pull this pin above 1.23V.
VCC (Pin 24)
Bias supply voltage for the controller. Connect this pin to a
5V power supply.
5
5 Page 
ISL6557
During the soft-start interval, the soft-start voltage, VRAMP,
increases linearly from zero to 140% of the programmed
DAC voltage. At the same time a current source, IRAMP, is
decreasing from 160µA down to zero. These signals are
connected as shown in Figure 9 (IOUT may or may not be
connected to FB depending on the particular application).
EXTERNAL CIRCUIT
RC
CC
COMP
ISL6557 INTERNAL CIRCUIT
RFB
FB
IOUT
VDIFF
ERROR AMPLIFIER
-
+ VCOMP
IRAMP
REFERENCE
VOLTAGE
IAVG
VRAMP
IDEAL DIODES
FIGURE 9. RAMP CURRENT AND VOLTAGE FOR
REGULATING SOFT-START SLOPE
AND DURATION
The ideal diodes in Figure 9 assure that the controller tries to
regulate its output to the lower of either the reference voltage or
VRAMP. Since IRAMP creates an initial offset across RFB of
RFB times 160mA, the first PWM pulses will not be seen until
VRAMP is greater than the RFB IRAMP offset. This produces a
delay after the ISL6557 enables before the output voltage starts
moving. For example, if VID = 1.5V, RFB = 1kΩ and
TSS = 8.3ms, the delay can be expressed using Equation 6.
tDELAY = -1----+------R---------F--------B1---T---.--1--4S----6----(S--0----V------×--I----D----1----)--0--------–------6-- = 580µs
(EQ. 6)
From this point, the soft-start ramps linearly until VRAMP
reaches VID. For the system described above, this first
linear ramp will continue for approximately
tRAMP1
=
T----S----S-- –
1.4
tDELAY
= 5.27ms
(EQ. 7)
The final portion of the soft-start sequence is the time
remaining after VRAMP reaches VID and before IRAMP gets to
zero. This is also characterized by a slight linear ramp in the
output voltage which, for the current example, exists for a time
tRAMP2 = TSS – tRAMP1 – tDELAY
= 2.34ms
(EQ. 8)
This behavior is seen in the example in Figure 10 of a converter
switching at 500kHz. For this converter, RFB is set to 2.67kΩ
leading to TSS = 4.0ms, tDELAY = 700ns, tRAMP1 = 2.23ms,
and tRAMP2 = 1.17ms.
VOUT, 500mV/DIV
EN, 5V/DIV
tDELAY tRAMP1 tRAMP2
1ms/DIV
FIGURE 10. SOFT-START WAVEFORMS FOR ISL6557 BASED
MULTI-PHASE BUCK CONVERTER
NOTE: Switching frequency 500kHz and RFB = 2.67kΩ
DYNAMIC VID
The ISL6557 is capable of executing on-the-fly output-
voltage changes. At the beginning of the phase-1 switching
cycle (defined in the section entitled PWM Operation), the
ISL6557 checks for a change in the VID code. The VID code
is the bit pattern present at pins VID4-VID0 as outlined in
Voltage Regulation. If the new code remains stable for
another full cycle, the ISL6557 begins incrementing the
reference by making 25mV change every two switching
cycles until the it reaches the new VID code.
01110
00110
VID, 5V/DIV
VID CHANGE OCCURS
ANYWHERE HERE
1.5V
VREF, 100mV/DIV
1.5V
VOUT, 100mV/DIV
5µs/DIV
FIGURE 11. DYNAMIC-VID WAVEFORMS FOR 500kHZ
ISL6557 BASED MULTI-PHASE BUCK
CONVERTER
Since the ISL6557 recognizes VID-code changes only at the
beginnings of switching cycles, up to one full cycle may pass
before a VID change registers. This is followed by a one-
cycle wait before the output voltage begins to change. Thus,
the total time required for a VID change, tDV, is dependent
on the switching frequency (fS), the size of the change
(∆VID), and the time before the next switching cycle begins.
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ISL6557.PDF ] | |
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