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PDF ISL6556B Data sheet ( Hoja de datos )

Número de pieza ISL6556B
Descripción Optimized Multi-Phase PWM Controller with 6-Bit DAC and Programmable Internal Temperature Compensation for VR10.X Application
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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®
Data Sheet
March 2003
ISL6556B
FN9097.1
Optimized Multi-Phase PWM Controller
with 6-Bit DAC and Programmable
Internal Temperature Compensation for
VR10.X Application
The ISL6556B controls microprocessor core voltage
regulation by driving up to 4 synchronous-rectified buck
channels in parallel. Multi-phase buck converter architecture
uses interleaved timing to multiply channel ripple frequency
and reduce input and output ripple currents.
The ISL6556B utilizes rDS(ON) current sensing in each
phase for adaptive voltage positioning (droop), channel-
current balancing, and over-current protection. To ensure
the accuracy of droop, a programmable internal temperature
compensation function is implemented to nullify the effect of
rDS(on) temperature sensitivity.
A unity gain, differential amplifier is provided for remote
voltage sensing. Any potential difference between remote
and local grounds can be eliminated using the remote-sense
amplifier. The precision threshold-sensitive enable input is
available to accurately coordinate the start up of the
ISL6556B with Intersil MOSFET driver IC. Dynamic-VID™
technology allows seamless on-the-fly VID changes. The
offset pin allows accurate voltage offset settings that are
independent of VID setting. The ISL6556B uses 5V bias and
has a built-in shunt regulator to allow 12V bias using only a
small external limiting resistor.
Pinouts
32-LEAD QFN
TOP VIEW
VID3 1
VID2 2
VID1 3
VID0 4
VID12.5 5
OFS 6
TCOMP 7
REF 8
24 PWM4
23 ISEN4
22 ISEN2
21 PWM2
20 PWM1
19 ISEN1
18 GND
17 ISEN3
Features
• Precision Multi-Phase Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.5% System Accuracy Over Temperature and Life
- Adjustable Reference-Voltage Offset
• Precision rDS(on) Current Sensing
- Integrated Programmable Temperature Compensation
- Accurate Load-Line Programming
- Accurate Channel-Current Balancing
- Low-Cost, Lossless Current Sensing
• Internal Shunt Regulator for 5V or 12V Biasing
• Microprocessor Voltage Identification Input
- Dynamic VID™ Technology
- 6-Bit VID Input
- 0.8375V to 1.600V in 12.5mV Steps
• Threshold Enable Function for Precision Sequencing
• Over Current Protection
• Over-Voltage Protection
- No Additional External Components Needed
- OVP Pin to drive opitional Crowbar Device
• 2, 3, or 4 Phase Operation up to 1.5MHz per Phase
• QFN Package Option
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
Flat No Leads - Product Outline
- QFN Near Chip Scale Package Footprint; Improves
PCB Efficiency, Thinner in Profile
Ordering Information
PART NUMBER TEMP. (oC) PACKAGE
ISL6556BCB
0 to 105 28-PIN SOIC
ISL6556BCR
0 to 105 32-PIN QFN
PKG. NO.
M28.3
L32.5X5B
OVP 1
PGOOD 2
VID4 3
VID3 4
VID2 5
VID1 6
VID0 7
VID12.5 8
OFS 9
TCOMP 10
REF 11
FB 12
COMP 13
VDIFF 14
28-PIN SOIC
TOP VIEW
28 FS
27 EN
26 VCC
25 PWM4
24 ISEN4
23 ISEN2
22 PWM2
21 PWM1
20 ISEN1
19 ISEN3
18 PWM3
17 GND
16 RGND
15 VSEN
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Dynamic VID™ is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved

1 page




ISL6556B pdf
Typical Application of ISL6556BCR
ISL6556B
+12V
+5V
FB
VDIFF
VSEN
RGND
COMP VCC
OFSOUT
TCOMP
PGOOD
OVP
REF
ISL6556BCR
VID4
VID3
VID2
ISEN1
PWM1
PWM2
VID1
ISEN2
VID0
VID12.5
PWM3
ISEN3
OFS
FS
GND ENLL
RT
PWM4
ISEN4
EN
+12V
VID_PGOOD
VCC BOOT
UGATE
PVCC
PHASE
HIP6601B
LGATE
PWM
GND
+12V
VCC BOOT
UGATE
PVCC
PHASE
HIP6601B
LGATE
PWM
GND
+12V
VCC BOOT
UGATE
PVCC
PHASE
HIP6601B
LGATE
PWM
GND
+12V
VCC BOOT
UGATE
PVCC
PHASE
HIP6601B
LGATE
PWM
GND
5
VIN
VIN
VIN
VIN
µP
LOAD

5 Page





ISL6556B arduino
ISL6556B
pulse width which corrects for any unbalance and drives the
error current toward zero. Figure 4 illustrates Intersil’s
patented current-balance method as implemented on
channel-1 of a multi-phase converter.
VCOMP
+
-
f(jω)
+
-
SAWTOOTH SIGNAL
IER
IAVG
-
÷N
+
Σ
PWM1
I4 *
I3 *
I2
I1
NOTE: *Channels 3 and 4 are optional.
FIGURE 4. CHANNEL-1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
Two considerations designers face are MOSFET selection
and inductor design. Both are significantly improved when
channel currents track at any load level. The need for
complex drive schemes for multiple MOSFETs, exotic
magnetic materials, and expensive heat sinks is avoided,
resulting in a cost-effective and easy-to-implement solution
relative to single-phase conversion. Channel-current
balance insures that the thermal advantage of multi-phase
conversion is realized. Heat dissipation in multiple channels
is spread over a greater area than can easily be
accomplished using the single phase approach.
In some circumstances, it may be necessary to deliberately
design some channel-current unbalance into the system. In
a highly compact design, one or two channels may be able
to cool more effectively than the other(s) due to nearby air
flow or heat sinking components. The other channel(s) may
have more difficulty cooling with comparatively less air flow
and heat sinking. The hotter channels may also be located
close to other heat-generating components tending to drive
their temperature even higher. In these cases, the proper
selection of the current sense resistors (RISEN in Figure 3)
introduces channel current unbalance into the system.
Increasing the value of RISEN in the cooler channels and
decreasing it in the hotter channels moves all channels into
thermal balance at the expense of current balance.
Voltage Regulation
The integrating compensation network shown in Figure 5
assures that the steady-state error in the output voltage is
limited only to the error in the reference voltage (output of
the DAC) and offset errors in the OFS current source,
remote-sense and error amplifiers. Intersil specifies the
guaranteed tolerance of the ISL6556B to include the
combined tolerances of each of these elements.
The output of the error amplifier, VCOMP, is compared to the
sawtooth waveform to generate the PWM signals. The PWM
signals control the timing of the Intersil MOSFET drivers and
regulate the converter output to the specified reference
voltage. The internal and external circuitry that controls
voltage regulation is illustrated in Figure 5.
EXTERNAL CIRCUIT
RC CC COMP
TCOMP
RTCOMP
REF
CREF
FB
RFB
+
VDROOP
-
VDIFF
ISL6556B INTERNAL CIRCUIT
VID DAC
1k
+
- VCOMP
ERROR AMPLIFIER
IAVG
VOUT+
VOUT-
VSEN
RGND
+
-
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
FIGURE 5. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADUJUSTMENT
The ISL6556B incorporates an internal differential remote-
sense amplifier in the feedback path. The amplifier removes
the voltage error encountered when measuring the output
voltage relative to the local controller ground reference point
resulting in a more accurate means of sensing output
voltage. Connect the microprocessor sense pins to the non-
inverting input, VSEN, and inverting input, RGND, of the
remote-sense amplifier. The remote-sense output, VDIFF, is
connected to the inverting input of the error amplifier through
an external resistor.
A digital to analog converter (DAC) generates a reference
voltage based on the state of logic signals at pins VID4
through VID12.5. The DAC decodes the a 6-bit logic signal
(VID) into one of the discrete voltages shown in Table 1.
Each VID input offers a 20µA pull-up to an internal 2.5V
source for use with open-drain outputs. The pull-up current
diminishes to zero above the logic threshold to protect
voltage-sensitive output devices. External pull-up resistors
can augment the pull-up current sources in case leakage
into the driving device is greater than 20µA.
11

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