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PDF ISL6553 Data sheet ( Hoja de datos )
| Número de pieza | ISL6553 | |
| Descripción | Microprocessor CORE Voltage Regulator Multi-Phase Buck PWM Controller | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ISL6553 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
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August 2004
ISL6553
FN4931.1
Microprocessor CORE Voltage Regulator
Multi-Phase Buck PWM Controller
The ISL6553 multi-phase PWM control IC together with its
companion gate drivers, the HIP6601, HIP6602 or HIP6603
provides a precision voltage regulation system for advanced
microprocessors. Multi-phase power conversion is a marked
departure from earlier single phase converter configurations
previously employed to satisfy the ever increasing current
demands of modern microprocessors. Multi-phase
converters, by distributing the power and load current results
in smaller and lower cost transistors with fewer input and
output capacitors. These reductions accrue from the higher
effective conversion frequency with higher frequency ripple
current due to the phase interleaving process of this
topology. For example, a two phase converter operating at
350kHz will have a ripple frequency of 700kHz. Moreover,
greater converter bandwidth of this design results in faster
response to load transients.
Outstanding features of this controller IC include
programmable VID codes from the microprocessor that
range from 1.05V to 1.825V with a system accuracy of 1%.
Pull up currents on these VID pins eliminates the need for
external pull up resistors. In addition “droop” compensation,
used to reduce the overshoot or undershoot of the CORE
voltage, is easily programmed with a single resistor.
Another feature of this controller IC is the PGOOD monitor
circuit which is held low until the CORE voltage increases,
during its Soft-Start sequence, to within 10% of the
programmed voltage. Over-voltage, 15% above
programmed CORE voltage, results in the converter shutting
down and turning the lower MOSFETs ON to clamp and
protect the microprocessor. Under voltage is also detected
and results in PGOOD low if the CORE voltage falls 10%
below the programmed level. Over-current protection
reduces the regulator RMS output current to 41% of the
programmed over-current trip value. These features provide
monitoring and protection for the microprocessor and power
system.
Features
• Multi-Phase Power Conversion
• Precision Channel Current Sharing
- Loss Less Current Sampling - Uses rDS(ON)
• Precision CORE Voltage Regulation
- 1% System Accuracy Over Temperature
• Microprocessor Voltage Identification Input
- 5-Bit VID Input
- 1.05V to 1.825V in 25mV Steps
- Programmable “Droop” Voltage
• Fast Transient Recovery Time
• Over Current Protection
• High Ripple Frequency, (Channel Frequency) Times
Number Channels . . . . . . . . . . . . . . . . . .100kHz to 3MHz
• Pb-free available
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Ordering Information
PART NUMBER TEMP. (oC) PACKAGE
ISL6553CB
0 to 70 16 Ld SOIC
ISL6553CBZ (Note)
0 to 70
16 Ld SOIC
(Pb-free)
ISL6553EVAL1
Evaluation Platform
*Add “-T” suffix to part number for tape and reel packaging.
PKG. DWG.
#
M16.15
M16.15
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish, which
is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
Pinout
ISL6553 (SOIC)
TOP VIEW
VID3 1
VID2 2
VID1 3
VID0 4
VID25mV 5
COMP 6
FB 7
FS/DIS 8
16 VCC
15 PGOOD
14 ISEN1
13 PWM1
12 PWM2
11 ISEN2
10 VSEN
9 GND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2000, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6553
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V
Input, Output, or I/O Voltage . . . . . . . . . GND -0.3V to VVCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class TBD
Recommended Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 5%
Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Thermal Information
Thermal Resistance (Typical, Note 1)
JA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
106
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications Operating Conditions: VCC = 5V, TA = 0oC to 70oC, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
INPUT SUPPLY POWER
Input Supply Current
POR (Power-On Reset) Threshold
RT = 100k, Active and Disabled Maximum Limit
VCC Rising
- 10
4.25 4.38
15
4.5
mA
V
VCC Falling
3.75 3.88 4.00 V
REFERENCE AND DAC
DAC Voltage Accuracy
DAC Pin Input Low Voltage Threshold
-1 - 1 %
- - 0.8 V
DAC Pin Input High Voltage Threshold
2.0 - - V
VID Pull-Up
OSCILLATOR
VIDx = 0V or VIDx = 3V
10 20 40 A
Frequency, FSW
Adjustment Range
RT = 100k, 1%
See Figure 10
245 275 305 kHz
0.05 -
1.5 MHz
Disable Voltage
ERROR AMPLIFIER
Maximum Voltage at FS/DIS to Disable Controller. IFS/DIS = 1mA
-
- 1.0 V
DC Gain
Gain-Bandwidth Product
Slew Rate
Maximum Output Voltage
Minimum Output Voltage
ISEN
RL = 10K to GND
CL = 100pF, RL = 10K to GND
CL = 100pF, Load = 400A
RL = 10K to GND, Load = 400A
RL = 10K to GND, Load = -400A
- 72 - dB
- 18 - MHz
- 5.3 - V/s
3.6 4.1
-
V
- 0.16 0.5
V
Full Scale Input Current
Over-Current Trip Level
POWER GOOD MONITOR
Under-Voltage Threshold
Under-Voltage Threshold
PGOOD Low Output Voltage
PROTECTION
VSEN Rising
VSEN Falling
IPGOOD = 4mA
- 50 -
- 82.5 -
A
A
- 0.92 - VDAC
- 0.90 - VDAC
- 0.18 0.4
V
Over-Voltage Threshold
Percent Over-Voltage Hysteresis
VSEN Rising
VSEN Falling after Over-Voltage
1.12 1.15 1.2 VDAC
-2-%
5
5 Page 
ISL6553
With a high dv/dt load transient, typical of high performance
microprocessors, the largest deviations in output voltage
occur at the leading and trailing edges of the load transient. In
order to fully utilize the output-voltage tolerance range, the
output voltage is positioned in the upper half of the range
when the output is unloaded and in the lower half of the range
when the controller is under full load. This droop
compensation allows larger transient voltage deviations and
thus reduces the size and cost of the output filter components.
RIN should be selected to give the desired “droop” voltage at
the normal full load current 50A applied through the RISEN
resistor (or at a different full load current if adjusted as under
“Over-current, Selecting RISEN” above).
RIN = VDROOP / 50A
For a VDROOP of 80mV, RIN = 1.6k
The AC feedback components, RFB and Cc, are scaled in
relation to RIN.
Current Balancing
The detected currents are also used to balance the phase
currents.
Each phase’s current is compared to the average of the two
phase currents, and the difference is used to create an offset
in that phase’s PWM comparator. The offset is in a direction
to reduce the imbalance.
The balancing circuit can not make up for a difference in
rDS(ON) between synchronous rectifiers. If a FET has a
higher rDS(ON), the current through that phase will be
reduced.
Figures 8 and 9 show the inductor current of a two phase
system without and with current balancing.
Inductor Current
The inductor current in each phase of a multi-phase Buck
converter has two components. There is a current equal to
the load current divided by the number of phases (ILT / n),
and a sawtooth current, (iPK-PK) resulting from switching.
The sawtooth component is dependent on the size of the
inductors, the switching frequency of each phase, and the
values of the input and output voltage. Ignoring secondary
effects, such as series resistance, the peak to peak value of
the sawtooth current can be described by:
iPK-PK = (VIN x VCORE - VCORE2) / (L x FSW x VIN)
Where: VCORE = DC value of the output or VID voltage
VIN = DC value of the input or supply voltage
L = value of the inductor
FSW = switching frequency
Example: For VCORE = 1.6V,
VIN = 12V,
L = 1.3H,
FSW = 250kHz,
Then iPK-PK = 4.3A
25
20
15
10
5
0
FIGURE 8. TWO CHANNEL multi-phase SYSTEM WITH
CURRENT BALANCING DISABLED
25
20
15
10
5
0
FIGURE 9. TWO CHANNEL multi-phase SYSTEM WITH
CURRENT BALANCING ENABLED
The inductor, or load current, flows alternately from VIN
through Q1 and from ground through Q2. The ISL6553
samples the on-state voltage drop across each Q2 transistor
to indicate the inductor current in that phase. The voltage
drop is sampled 1/3 of a switching period, 1/FSW, after Q1 is
turned OFF and Q2 is turned on. Because of the sawtooth
current component, the sampled current is different from the
average current per phase. Neglecting secondary effects,
the sampled current (ISAMPLE) can be related to the load
current (ILT) by:
ISAMPLE = ILT / n + (VINVCORE - 3VCORE2) / (6L x FSW x VIN)
Where: ILT = total load current
n = the number of channels
Example: Using the previously given conditions, and
For ILT = 50A,
n =2
Then ISAMPLE = 25.49A
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ISL6553.PDF ] | |
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