|
|
PDF ISL6539 Data sheet ( Hoja de datos )
| Número de pieza | ISL6539 | |
| Descripción | Wide Input Range Dual PWM Controller with DDR Option | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ISL6539 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
|
No Preview Available !
®
Data Sheet
Wide Input Range Dual PWM Controller
with DDR Option
The ISL6539 dual PWM controller delivers high efficiency and
tight regulation from two voltage regulating synchronous buck
DC/DC converters. It was designed especially for DDR DRAM,
SDRAM, graphic chipset applications, and system regulators in
high performance applications.
Voltage-feed-forward ramp modulation, current mode
control, and internal feedback compensation provide fast
response to input voltage and output load transients. Input
current ripple is minimized by channel-to-channel PWM
phase shift of 0°, 90°, or 180° (determined by input voltage
and status of the DDR pin).
The ISL6539 can control two independent output voltages
adjustable from 0.9V to 5.5V or, by activating the DDR pin,
transform into a complete DDR memory power supply
solution. In DDR mode, CH2 output voltage VTT tracks CH1
output voltage VDDQ. CH2 output can both source and sink
current, an essential power supply feature for DDR memory.
The reference voltage VREF required by DDR memory is
generated as well.
In dual power supply applications the ISL6539 monitors the
output voltage of both CH1 and CH2. An independent
PGOOD (power good) signal is asserted for each channel
after the soft-start sequence has completed, and the output
voltage is within PGOOD window. In DDR mode CH1
generates the only PGOOD signal.
Built-in overvoltage protection prevents the output from going
above 115% of the set point by holding the lower MOSFET on
and the upper MOSFET off. When the output voltage decays
below the overvoltage threshold, normal operation
automatically resumes. Once the soft-start sequence has
completed, undervoltage protection latches the offending
channel off if the output drops below 75% of its set point value
for the dual switcher. Adjustable overcurrent protection (OCP)
monitors the voltage drop across the rDS(ON) of the lower
MOSFET. If more precise current-sensing is required, an
external current sense resistor may be used.
ISL6539
May 2004
FN9144.3
Features
• Provides regulated output voltage in the range 0.9V–5.5V
• Complete DDR memory power solution with VTT tracks
VDDQ/2 and VDDQ/2 buffered reference output
• Supports both DDR-I and DDR2 memory
• Lossless rDS(ON) current-sense sensing
• Excellent dynamic response with voltage feed-forward and
current mode control accommodating wide range LC filter
selections
• Dual mode operation–operates directly from a 5.0-15V
input or 3.3V/5V system rail
• Undervoltage lock-out on VCC pin
• Power-good, overcurrent, overvoltage, undervoltage
protection for both channels
• Synchronized 300kHz PWM operation in PWM mode
• Pb-Free Available
Applications
• Single and Dual Channel DDR Memory Power Systems
• Graphics cards - GPU and memory supplies
• Supplies for Servers, Motherboards, FPGAs
• ASIC power supplies
• Embedded processor and I/O supplies
• DSP supplies
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6539
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
PWM CONVERTERS
Load Regulation
VSEN pin bias current
Minimum Duty Cycle
Maximum Duty Cycle
Undervoltage Shut-Down Level
Overvoltage Protection
GATE DRIVERS
IVSEN
DMIN
DMAX
VUVL
VOVP1
0.0mA < IVOUT1 < 5.0A; 5.0V < VIN < 15.0V
By design
Fraction of the set point; ~2ms noise filter
Fraction of the set point; ~2ms noise filter
-2.0
-
-
-
70
110
Upper Drive Pull-Up Resistance
R2UGPUP
Upper Drive Pull-Down Resistance
R2UGPDN
Lower Drive Pull-Up Resistance
R2LGPUP
Lower Drive Pull-Down Resistance
R2LGPDN
POWER GOOD AND CONTROL FUNCTIONS
VCC = 5V
VCC = 5V
VCC = 5V
VCC = 5V
-
-
-
-
Power Good Lower Threshold
Power Good Higher Threshold
PGOODx Leakage Current
PGOODx Voltage Low
ISEN sourcing current
VPG-
VPG+
IPGLKG
VPGOOD
Fraction of the set point; ~3ms noise filter
Fraction of the set point; ~3ms noise filter.
VPULLUP = 5.5V
IPGOOD = -4mA
By design
84
110
-
-
-
OCSET sourcing current range
2
EN - Low (Off)
-
EN - High (On)
2.0
DDR - Low (Off)
-
DDR - High (On)
3
DDR REF Output Voltage
DDR REF Output Current
VDDREF DDR = 1, IREF = 0...10mA
IDDREF DDR = 1. Guaranteed by design.
0.99*
VOC2
-
TYP
-
80
4
87
75
115
4
2.3
4
1.1
89
115
-
0.5
-
-
-
-
-
-
VOC2
10
MAX UNITS
+2.0
-
-
-
80
-
%
nA
%
%
%
%
8Ω
4Ω
8Ω
3Ω
92
120
1
1
260
20
0.8
-
0.8
-
1.01*
VOC2
12
%
%
µA
V
µA
µA
V
V
V
V
V
mA
Functional Pin Description
GND (Pin 1, 9, 20)
Signal ground for the IC. All three ground pins must be
connected to ground for proper IC operation. Connect to the
ground plane through a path as low in inductance as
possible.
LGATE1, LGATE2 (Pin 2, 27)
Connect these pins to the gates of the corresponding lower
MOSFETs. These pins provide the PWM-controlled gate
drive for the lower MOSFETs.
PGND1, PGND2 (Pin 3, 26)
These pins provide the return connection for lower gate
drivers, and are connected to sources of the lower
MOSFETs of their respective converters. These pins must
be connected to the ground plane through a path as low in
inductance as possible.
PHASE1, PHASE2 (Pin 4, 25)
The PHASE1 and PHASE2 points are the junction points of
the upper MOSFET sources, output filter inductors, and
lower MOSFET drains. Connect these pins to the respective
converter’s upper MOSFET source.
UGATE1, UGATE2 (Pin 5, 24)
Connect these pins to the gates of the corresponding upper
MOSFETs. These pins provide the PWM-controlled gate
drive for the upper MOSFETs.
BOOT1, BOOT2 (Pin 6, 23)
These pins power the upper MOSFET drivers of the PWM
converter. Connect these pins to the junction of the bootstrap
capacitor with the cathode of the bootstrap diode. The anode
of the bootstrap diode is connected to the VCC voltage.
5
5 Page 
ISL6539
TABLE 1. PWM COMPARATOR RAMP AMPLITUDE FOR
DUAL SWITCHER APPLICATION
VIN PIN CONNECTIONS
VRAMP
AMPLITUDE
Ch1 and Ch2 Input Voltage Input voltage >4.2V
Vin/8
Input voltage <4.2V
1.25V
GND
1.25V
TABLE 2. PWM COMPARATOR RAMP VOLTAGE AMPLITUDE
FOR DDR APPLICATION
VIN PIN CONNECTION
VRAMP
AMPLITUDE
Ch1 Input Voltage
Input voltage >4.2V
Vin/8
Input voltage <4.2V
1.25V
GND
1.25V
Ch2 Input voltage >4.2V
0.625V
GND
1.25V
The small signal transfer function from the error amplifier
output voltage Vc to the output voltage Vo can be written in
the following expression:
G(s)
=
Gm
R-----i---+-----D----RC----o-R------+-----R-----o-
--------------------W-------s------z------+-----1---------------------
W------s-p---1--
+
1
W------s-p---2--
+
1
The dc gain is derived by shorting the inductor and opening
the capacitor. There is one zero and two poles in this transfer
function.
The zero is related to ESR and the output capacitor.
The first pole is a low frequency pole associated with the
output capacitor and its charging resistors. The inductor can
be regarded as short. The second pole is the high frequency
pole related to the inductor. At high frequency the output cap
can be regarded as a short circuit. By approximation, the
poles and zero are inversely proportional to the time
constants, associated with inductor and capacitor, by the
following expressions:
Wz = -E----S----R--1---*---C-----o-
Wp1 = -(--E----S-----R------+-----(--R-----i--+-----D-1----C-----R-----)---|-|---R----o----)--*---C-----o-
Wp2 = R-----i---+-----D----C-----R-----L-+--o---E----S-----R------|-|---R----o--
Since the current loop separates the LC resonant poles into
two distant poles, and ESR zero tends to cancel the high
frequency pole, the second order system behaves like a first
order system. This control method simplifies the design of
the internal compensator and makes it possible to
accommodate many applications having a wide range of
parameters. The schematics for the internal compensator is
shown in Figure 6.
1.25pF
500K
TO PWM
COMPARATOR
4.4K
ISEN
1M 16.7pF
-
Vc +
300K
0.9V
VSEN
FIGURE 6. THE INTERNAL COMPENSATOR
Its transfer function can be written as the following:
Gcomp(s) = 1----.-8----5---7-----•----1----0---5--s----2----2-------π-----π---s---f---s---fz------p---1-----1-----+-+---1--1---------2-------π-----s--f----z------2------+-----1----
where
fz1 = 6.98kHz, fz2 = 380kHz, and fp1 = 137kHz
Outside the ISL6539 chip, a capacitor Cz can be placed in
parallel with the top resistor in the feedback resistor divider,
as shown in Figure 4. In this case the transfer function from
the output voltage to the middle point of the divider can be
written as:
Gfd(s) = R-----1--R---+--2--R-----2- -s---(--R---s--1--R--|--|1--R--C---2-z--)--+-C----z1----+-----1--
The ratio of R1 and R2 is determined by the output voltage
set point; therefore, the position of the pole and zero
frequency in the above equation may not be far apart;
however, they can improve the loop gain and phase margin
with the proper design.
The Cz can bring the high frequency transient output voltage
variation directly to the VSEN pin to cause the PGOOD drop.
Such an effect should be considered in the selection of Cz.
From the analysis above, the system loop gain can be
written as:
Gloop(s) = G(s) • Gcomp(s) • Gfd(s)
Figure 7 shows the composition of the system loop gain. As
shown in the graph, the power stage became a well damped
second order system compared to the LC filter
characteristics. The ESR zero is so close to the high
frequency pole that they cancel each other out. The power
stage behaves like a first order system. With an internal
compensator, the loop gain transfer function has a cross
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ISL6539.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ISL6530 | Dual 5V Synchronous Buck Pulse-Width Modulator (PWM) Controller for DDRAM Memory VDDQ and VTT Termination | Intersil Corporation |
| ISL6531 | Dual 5V Synchronous Buck Pulse-Width Modulator (PWM) Controller for DDRAM Memory VDDQ and VTT Termination | Intersil Corporation |
| ISL6532 | ACPI Regulator/Controller for Dual Channel DDR Memory Systems | Intersil Corporation |
| ISL6532A | ACPI Regulator/Controller for Dual Channel DDR Memory Systems | Intersil Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |