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PDF ISL6532B Data sheet ( Hoja de datos )
| Número de pieza | ISL6532B | |
| Descripción | ACPI Regulator/Controller for Dual Channel DDR Memory Systems | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
December 2003
ISL6532B
FN9120.2
ACPI Regulator/Controller for
Dual Channel DDR Memory Systems
The ISL6532B provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 memory
systems. Included are both a synchronous buck controller
and integrated LDO to supply VDDQ with high current during
S0/S1 states and standby current during S3 state. During
Run mode, a fully integrated sink-source regulator generates
an accurate (VDDQ/2) high current VTT voltage without the
need for a negative supply. A buffered version of the VDDQ/2
reference is provided as VREF.
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. Both the switching
regulator and integrated standby LDO provide a maximum
static regulation tolerance of ±2% over line, load, and
temperature ranges. The output is user-adjustable by means
of external resistors down to 0.8V.
Switching the memory core output between the PWM
regulator and the standby LDO during state transitions is
accomplished smoothly via the internal ACPI control
circuitry. The NCH signal provides synchronized switching of
a backfeed blocking switch during the transitions eliminating
the need to route 5V Dual to the memory supply.
An integrated soft-start feature brings VDDQ into regulation
in a controlled manner when returning to S0/S1 state from
S4/S5 or mechanical off states. During S0 the PGOOD
signal indicates that all supplies are within spec and
operational.
Each output is monitored for under and over-voltage events.
Current limiting is included on the VTT and VDDQ standby
regulators. Thermal shutdown is integrated.
Pinout
ISL6532B (QFN)
TOP VIEW
20 19 18 17 16
5VSBY 1
GND 2
VTT 3
VTT 4
VDDQ 5
15 NCH
14 PGOOD
13 GND
12 COMP
11 FB
6 7 8 9 10
Features
• Generates 2 Regulated Voltages
- Synchronous Buck PWM Controller with Standby LDO
- 3A Integrated Sink/Source Linear Regulator with
Accurate VDDQ/2 Divider Reference
- Glitch-free Transitions During State Changes
• ACPI Compliant Sleep State Control
• Integrated VREF Buffer
• PWM Controller Drives Low Cost N-Channel MOSFETs
• 250kHz Constant Frequency Operation
• Tight Output Voltage Regulation
- Both Outputs: ±2% Over Temperature
• 5V or 3.3V Down Conversion
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Over Current Protection on VTT and Under/Over-Voltage
Monitoring of Both Outputs
• Integrated Thermal Shutdown Protection
• QFN Package Option
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
Flat No Leads - Product Outline
- QFN Near Chip Scale Package Footprint; Improves
PCB Efficiency, Thinner in Profile
Applications
• Single and Dual Channel DDR Memory Power Systems in
ACPI compliant PCs
• Graphics cards - GPU and memory supplies
• ASIC power supplies
• Embedded processor and I/O supplies
• DSP supplies
Ordering Information
TEMP. RANGE
PART NUMBER
(oC)
PACKAGE PKG. DWG. #
ISL6532BCR
0 to 70 20 Ld 6x6 QFN L20.6x6
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6532B
Absolute Maximum Ratings
5VSBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +7V
P12V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14V
UGATE, LGATE, NCH . . . . . . . . . . . . . . GND - 0.3V to P12V + 0.3V
All other Pins . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5VSBY + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 2
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) θJA (oC/W) θJC (oC/W)
QFN Package . . . . . . . . . . . . . . . . . . .
32
5
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Recommended Operating Conditions
Supply Voltage on 5VSBY . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
Supply Voltage on P12V . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
Supply Voltage on 3V3SBY . . . . . . . . . . . . . . . . . . . . . +3.3V ±10%
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Junction Temperature Range . . . . . . . . . . . . . . . . . . 0oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
5VSBY SUPPLY CURRENT
Nominal Supply Current
ICC_S0
ICC_S3
S3# & S5# HIGH, UGATE/LGATE Open
S3# LOW, S5# HIGH, UGATE/LGATE
Open
3.00 5.25 7.25
3.50 - 4.75
mA
mA
ICC_S5
S5# LOW, S3# Don’t Care,
UGATE/LGATE Open
300 - 800
µA
POWER-ON RESET
Rising 5VSBY POR Threshold
4.00 - 4.35
V
Falling 5VSBY POR Threshold
3.60 - 3.95
V
Rising P12V POR Threshold
10.0 - 10.5
V
Falling P12V POR Threshold
8.80 - 9.75
V
OSCILLATOR AND SOFT-START
PWM Frequency
Ramp Amplitude
Error Amp Reset Time
VDDQ Soft-Start Interval
REFERENCE VOLTAGE
fOSC
∆VOSC
tRESET
tSS
S5# LOW to S5# HIGH
S5# LOW to S5# HIGH
220 250 280
- 1.5 -
6.5 - 9.5
6.5 - 9.5
kHz
V
ms
ms
Reference Voltage
System Accuracy
VREF
- 0.800 -
-2.0 - +2.0
V
%
PWM CONTROLLER ERROR AMPLIFIER
DC Gain
Guaranteed By Design
- 80 -
dB
Gain-Bandwidth Product
GBWP
15 -
- MHz
Slew Rate
SR
- 6 - V/µs
STATE LOGIC
S3# Transition Level
S5# Transition Level
VS3
VS5
- 1.5 -
- 1.5 -
V
V
5
5 Page 
ISL6532B
∆ VOSC
OSC
PWM
COMPARATOR
-
+
DRIVER
DRIVER
VIN
LO
PHASE CO
VDDQ
ZFB
VE/A
-
+
ZIN
ERROR REFERENCE
AMP
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C1
C2 R2
ZFB VDDQ
ZIN
C3 R3
COMP
R1
- FB
+
ISL6532B
REFERENCE
R4
VDDQ
=
0.8
×
1
+
RR-----14-
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
The compensation network consists of the error amplifier
(internal to the ISL6532B) and the impedance networks ZIN
and ZFB. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f0dB and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 5. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth.
2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC).
3. Place 2ND Zero at Filter’s Double Pole.
4. Place 1ST Pole at the ESR Zero.
5. Place 2ND Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
FZ1 = -2---π------x-----R--1--2-----x------C----2-
FZ2 = 2----π------x-----(--R-----1----+-1----R-----3---)----x-----C-----3-
FP1
=
---------------------------1-----------------------------
2π
x
R2
x
C-C----11-----+x-----CC----2-2-
FP2 = -2---π------x-----R--1--3-----x------C----3-
Figure 6 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high
gain peak due to the high Q factor of the output filter and is
not shown in Figure 6. Using the above guidelines should
give a Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at FP2 with the
capabilities of the error amplifier. The Closed Loop Gain is
constructed on the graph of Figure 6 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
This is equivalent to multiplying the modulator transfer
function to the compensation transfer function and plotting
the gain.
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW)
overall loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
100 FZ1 FZ2 FP1 FP2
80
OPEN LOOP
60 ERROR AMP GAIN
40
20LOG
20 (R2/R1)
20LOG
0 (VIN/∆VOSC)
MODULATOR
-20 GAIN
-40
FLC FESR
-60
10 100 1K 10K 100K
COMPENSATION
GAIN
CLOSED LOOP
GAIN
1M 10M
FREQUENCY (Hz)
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Output Voltage Selection
The output voltage of the VDDQ PWM converter can be
programmed to any level between VIN and the internal
reference, 0.8V. An external resistor divider is used to scale
the output voltage relative to the reference voltage and feed
it back to the inverting input of the error amplifier, see
Figure 6.
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ISL6532B.PDF ] | |
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