DataSheet.jp

ISL6532 の電気的特性と機能

ISL6532のメーカーはIntersil Corporationです、この部品の機能は「ACPI Regulator/Controller for Dual Channel DDR Memory Systems」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL6532
部品説明 ACPI Regulator/Controller for Dual Channel DDR Memory Systems
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




このページの下部にプレビューとISL6532ダウンロード(pdfファイル)リンクがあります。

Total 14 pages

No Preview Available !

ISL6532 Datasheet, ISL6532 PDF,ピン配置, 機能
®
Data Sheet
December 2003
ISL6532
FN9112.2
ACPI Regulator/Controller for
Dual Channel DDR Memory Systems
The ISL6532 provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 memory
systems. Included are both a synchronous buck controller
and integrated LDO to supply VDDQ with high current during
S0/S1 states and standby current during S3 state. During
Run mode, a fully integrated sink-source regulator generates
an accurate (VDDQ/2) high current VTT voltage without the
need for a negative supply. A buffered version of the VDDQ/2
reference is provided as VREF.
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. Both the switching
regulator and integrated standby LDO provide a maximum
static regulation tolerance of ±2% over line, load, and
temperature ranges. The output is user-adjustable by means
of external resistors down to 0.8V.
Switching the memory core output between the PWM
regulator and the standby LDO during state transitions is
accomplished smoothly via the internal ACPI control
circuitry. The NCH signal provides synchronized switching of
a backfeed blocking switch during the transitions eliminating
the need to route 5V Dual to the memory supply.
An integrated soft-start feature brings VDDQ into regulation in
a controlled manner when returning to S0/S1 state from
S4/S5 or mechanical off states. During S0 the PGOOD signal
indicates that all supplies are within spec and operational.
Each output is monitored for under and over-voltage events.
Current limiting is included on the VTT and VDDQ standby
regulators. Thermal shutdown is integrated.
Pinout
ISL6532 (QFN) TOP VIEW
20 19 18 17 16
5VSBY 1
GND 2
VTT 3
VTT 4
VDDQ 5
GND
21
15 NCH
14 PGOOD
13 GND
12 COMP
11 FB
6 7 8 9 10
Features
• Generates 2 Regulated Voltages
- Synchronous Buck PWM Controller with Standby LDO
- 3A Integrated Sink/Source Linear Regulator with
Accurate VDDQ/2 Divider Reference.
- Glitch-free Transitions During State Changes
• ACPI Compliant Sleep State Control
• Integrated VREF Buffer
• PWM Controller Drives Low Cost N-Channel MOSFETs
• 250kHz Constant Frequency Operation
• Tight Output Voltage Regulation
- Both Outputs: ±2% Over Temperature
• 5V or 3.3V Down Conversion
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Over Current Protection and Under/Over-Voltage
Monitoring of Both Outputs
• Integrated Thermal Shutdown Protection
• QFN Package Option
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
Flat No Leads - Product Outline
- QFN Near Chip Scale Package Footprint; Improves
PCB Efficiency, Thinner in Profile
Applications
Single and Dual Channel DDR Memory Power Systems in
ACPI compliant PCs
Graphics cards - GPU and memory supplies
• ASIC power supplies
• Embedded processor and I/O supplies
• DSP supplies
Ordering Information
TEMP. RANGE
PART NUMBER
(oC)
PACKAGE
ISL6532CR
0 to 70 20 Ld 6x6 QFN
PKG.
DWG. #
L20.6x6
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL6532 pdf, ピン配列
ISL6532
Simplified Power System Diagram
5VSBY
12V
SLP_S3
SLP_S5
5VSBY/3V3SBY
SLEEP
STATE
LOGIC
PWM
CONTROLLER
ISL6532
STANDBY
LDO
VTT
REGULATOR
5V
Q1
VDDQ
+
Q2
VREF
VTT
+
Typical Application - 5V or 3.3V Input
+3.3V CBP
5VSBY
+12V
VREF
PGOOD
VDDQ
SLP_S3
S3#
SLP_S5
S5#
VREF_OUT
VREF_IN
+
CSS
VTT
+
CVTT
VTT
VTT
VTTSNS
ISL6532
NCH
UGATE
LGATE
VDDQ
VDDQ
FB
COMP
+5V OR +3.3V
RNCH
+
CIN
Q1
LOUT
Q2
VDDQ
2.5V
+
CVDDQ
GND
3


3Pages


ISL6532 電子部品, 半導体
ISL6532
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
PWM CONTROLLER GATE DRIVERS
UGATE and LGATE Source
UGATE and LGATE Sink
NCH BACKFEED CONTROL
IGATE
IGATE
- -0.8 -
- 0.8 -
A
A
NCH Current Sink
NCH Trip Level
VDDQ STANDBY LDO
INCH
VNCH
NCH = 0.8V
- -6
9.0 9.5 10
mA
V
Output Drive Current
P5VSBY = 5.0V
- - 650 mA
P5VSBY = 3.3V
- - 550 mA
VTT REGULATOR
Upper Divider Impedance
Lower Divider Impedance
VREF_OUT Buffer Source Current
Maximum VTT Load Current
RU - 2.5 -
RL - 2.5 -
IVREF_OUT
- -2
IVTT_MAX
Periodic load applied with 30% duty cycle -3
-
3
and 10ms period using ISL6532EVAL1
evaluation board (see Application Note
AN1055)
k
k
mA
A
PGOOD
PGOOD Rising Threshold
PGOOD Falling Threshold
PROTECTION
VVTTSNS/VVDDQ S3# & S5# HIGH
VVTTSNS/VVDDQ S3# & S5# HIGH
- 57.5 -
- 45.0 -
%
%
VDDQ OV Level
VDDQ UV Level
Thermal Shutdown Limit
VFB/VREF
VFB/VREF
TSD
S3# & S5# HIGH
S3# & S5# HIGH
By Design
- 115 -
- 85 -
- 140 -
%
%
°C
Functional Pin Description
5VSBY (Pin 1)
5VSBY is the bias supply of the ISL6532. It is typically
connected to the 5V standby rail of an ATX power supply.
During S4/S5 sleep states the ISL6532 enters a reduced
power mode and draws less than 1mA (ICC5) from the
5VSBY supply. This pin should be locally bypassed using a
0.1µF capacitor.
P12V (Pin 18)
P12V provides the gate drive current to the switching
MOSFETs of the PWM power stage. The VTT regulation
circuit is also powered by P12V. P12V is only required
during S0/S1/S2 operation. P12V is typically connected to
the +12V rail of an ATX power supply.
P5VSBY (Pin 8)
This pin provides the VDDQ output power during the S3
sleep state. The regulator is capable of providing standby
VDDQ power from either a 5V or 3.3V source.
GND (Pin 2, 13, 21)
The GND terminals of the ISL6532 provide the return path
for the VTT LDO, Standby LDO and switching MOSFET gate
drivers. High ground currents are conducted directly through
the exposed paddle of the QFN package which must be
electrically connected to the ground plane through a path as
low in inductance as possible.
UGATE (Pin 20)
UGATE drives the upper (control) FET of the VDDQ
synchronous buck switching regulator. UGATE is driven
between GND and P12V.
LGATE (Pin 19)
LGATE drives the lower (synchronous) FET of the VDDQ
synchronous buck switching regulator. LGATE is driven
between GND and P12V.
6

6 Page



ページ 合計 : 14 ページ
 
PDF
ダウンロード
[ ISL6532 データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
ISL6530

Dual 5V Synchronous Buck Pulse-Width Modulator (PWM) Controller for DDRAM Memory VDDQ and VTT Termination

Intersil Corporation
Intersil Corporation
ISL6531

Dual 5V Synchronous Buck Pulse-Width Modulator (PWM) Controller for DDRAM Memory VDDQ and VTT Termination

Intersil Corporation
Intersil Corporation
ISL6532

ACPI Regulator/Controller for Dual Channel DDR Memory Systems

Intersil Corporation
Intersil Corporation
ISL6532A

ACPI Regulator/Controller for Dual Channel DDR Memory Systems

Intersil Corporation
Intersil Corporation


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap