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PDF ISL6531 Data sheet ( Hoja de datos )
| Número de pieza | ISL6531 | |
| Descripción | Dual 5V Synchronous Buck Pulse-Width Modulator (PWM) Controller for DDRAM Memory VDDQ and VTT Termination | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
July 2003
ISL6531
FN9053.1
Dual 5V Synchronous Buck Pulse-Width
Modulator (PWM) Controller for DDRAM
Memory VDDQ and VTT Termination
The ISL6531 provides complete control and protection for
dual DC-DC converters optimized for high-performance
DDRAM memory applications. It is designed to drive low
cost N-channel MOSFETs in synchronous-rectified buck
topology to efficiently generate 2.5V VDDQ for powering
DDRAM memory, VREF for DDRAM differential signalling,
and VTT for signal termination. The ISL6531 integrates all of
the control, output adjustment, monitoring and protection
functions into a single package.
The VDDQ output of the converter is maintained at 2.5V
through an integrated precision voltage reference. The VREF
output is precisely regulated to 1/2 the memory power
supply, with a maximum tolerance of ±1% over temperature
and line voltage variations. VTT accurately tracks VREF.
During V2_SD sleep mode, the VTT output is maintained by
a low power window regulator.
The ISL6531 provides simple, single feedback loop, voltage-
mode control with fast transient response for the VDDQ
regulator. The VTT regulator features internal compensation
that eases the design. It includes two phase-locked 300kHz
triangle-wave oscillators which are displaced 90o to
minimize interference between the two PWM regulators. The
regulators feature error amplifiers with a 15MHz gain-
bandwidth product and 6V/µs slew rate which enables high
converter bandwidth for fast transient performance. The
resulting PWM duty ratio ranges from 0% to 100%.
The ISL6531 protects against overcurrent conditions by
inhibiting PWM operation. The ISL6531 monitors the current
in the VDDQ regulator by using the rDS(ON) of the upper
MOSFET which eliminates the need for a current sensing
resistor.
Ordering Information
TEMP
PART NUMBER RANGE(oC) PACKAGE PKG. DWG. #
ISL6531CB
0 to 70 24 Lead SOIC M24.3
ISL6531CR
0 to 70 32 Lead 5x5 QFN L32.5x5
ISL6530/31EVAL1 Evaluation Board
Features
• Provides VDDQ, VREF, and VTT voltages for one- and
two- channel DDRAM memory systems
• Excellent voltage regulation
- VDDQ = 2.5V ±2% over full operating range
-
VREF =
1--
2
⋅
VDDQ
±1%
over
full
operating
range
- VTT = VREF ± 30mV
• Supports ‘S3’ sleep mode
-
VTT is held
regulator to
amt in12--im⋅ VizDeDwQakveia-uaplotiwmepower
window
• Fast transient response
- Full 0% to 100% duty ratio
• Operates from +5V Input
• VTT regulator internally compensated
• Overcurrent fault monitor on VDD
- Does not require extra current sensing element
- Uses MOSFET’s rDS(ON)
• Drives inexpensive N-Channel MOSFETs
• Small converter size
- 300kHz fixed frequency oscillator
• 24 Lead, SOIC or 32 Lead, 5mm×5mm QFN
Applications
• VDDQ, VTT, and VREF regulation for DDRAM memory
systems
- Main memory in AMD® Athlon™ and K8™, Pentium®
III, Pentium IV, Transmeta, PowerPC™, AlphaPC™,
and UltraSparc® based computer systems
• High-power tracking DC-DC regulators
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6531
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Boot Voltage, VBOOTn - VPHASEn. . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Junction Temperature Range . . . . . . . . . . . . . . . . . . . 0oC to 125oC
Thermal Information
Thermal Resistance
θJA (oC/W) θJC (oC/W)
SOIC Package (Note 1) . . . . . . . . . . . .
65
N/A
QFN Package (Note 2). . . . . . . . . . . . .
33
4
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead tips only)
For Recommended soldering conditions see Tech Brief TB389.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θJC, the
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications Recommended Operating Conditions with Vcc = 5V, unless otherwise noted.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP
VCC SUPPLY CURRENT
Nominal Supply
ICC OCSET/SD=VCC; UGATE1, UGATE2,
LGATE1, and LGATE2 Open
-5
Shutdown Supply
OCSET/SD=0V
-3
POWER-ON RESET
Rising VCC Threshold
Falling VCC Threshold
OSCILLATOR
VOCSET/SD=4.5V
VOCSET/SD=4.5V
4.25 -
3.75 -
Free Running Frequency
REFERENCES
VCC=5
275 300
Reference Voltage
(V2 Error Amp Reference)
VVREF SENSE1=2.5V
49.5 50.0
V1 Error Amp Reference Voltage
Tolerance
--
V1 Error Amp Reference
ERROR AMPLIFIERS
VREF VCC=5
- 0.8
DC Gain
- 82
Gain-Bandwidth Product
GBW
- 15
Slew Rate
SR COMP=10pF
-6
WINDOW REGULATOR
Load Current
- ±10
Output Voltage Error
V2_SD=VCC; ±10mA load on V2
- ±7
GATE DRIVERS
Upper Gate Source (UGATE1 and 2)
Upper Gate Sink (UGATE1 and 2)
Lower Gate Source (LGATE1 and 2)
Lower Gate Sink (LGATE1 and 2)
PROTECTION
IUGATE
IUGATE
ILGATE
ILGATE
VCC=5V, VUGATE=2.5V
VUGATE-PHASE=2.5V
VCC=5V, VLGATE=2.5V
VLGATE=2.5V
- -1
-1
- -1
-2
OCSET/SD Current Source
OCSET/SD Disable Voltage
IOCSET
VRESET
VOCSET=4.5VDC
34 40
- 0.8
MAX UNITS
- mA
- mA
4.5 V
4.0 V
325 kHz
50.5 %SENSE1
2%
-V
- dB
- MHz
- V/µs
- mA
-%
-A
-A
-A
-A
46 µA
-V
5
5 Page 
ISL6531
nodes. Use copper filled polygons on the top and bottom
circuit layers for the phase nodes. Use the remaining printed
circuit layers for small signal wiring. The wiring traces from
the GATE pins to the MOSFET gates should be kept short
and wide enough to easily handle the 1A of drive current.f
ISL6531
+5V VIN
VCC
CBP
GND
D1
CIN
BOOT1
UGATE1
PHASE1
LGATE1
PGND1
COMP1
FB1
CBOOT1
Q1
PHASE1
LOUT1
VDDQ
Q2
COUT1
C2A
R2A
C1A
R1A
R4 C3A R3A
SENSE1
+5V VIN
BOOT2
UGATE2
PHASE2
LGATE2
PGND2
D2 VDDQ
CBOOT2
Q3
PHASE2
LOUT2
VTT
Q4
COUT2
SENSE2
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 7. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
The switching components should be placed close to the
ISL6531 first. Minimize the length of the connections
between the input capacitors, CIN, and the power switches
by placing them nearby. Position both the ceramic and bulk
input capacitors as close to the upper MOSFET drain as
possible. Position the output inductor and output capacitors
between the upper MOSFET and lower diode and the load.
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Position the bypass capacitor, CBP, close to
the VCC pin with a via directly to the ground plane. Place the
PWM converter compensation components close to the FB
and COMP pins. The feedback resistors for both regulators
should also be located as close as possible to the relevant
FB pin with vias tied straight to the ground plane as required.
VDDQ Feedback Compensation
This section discusses the feedback compensation of the
VDDQ regulator. Figure 8 highlights the voltage-mode
control loop for a synchronous-rectified buck converter.
The output voltage (VOUT) is regulated to the Reference
voltage level. The error amplifier (error amp) output (VE/A)
is compared with the oscillator (OSC) triangular wave to
provide a pulse-width modulated (PWM) wave with an
amplitude of VIN at the PHASE node. The PWM wave is
smoothed by the output filter (LO and CO).
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A. This function is dominated by a DC
gain and the output filter (LO and CO), with a double pole
break frequency at FLC and a zero at FESR. The DC gain of
the modulator is simply the input voltage (VIN) divided by the
peak-to-peak oscillator voltage ∆VOSC.
OSC
PWM
DRIVER
COMPARATOR
D VOSC
+- DRIVER
VIN
LO
PHASE CO
VOUT
ZFB
VE/A
+-
ZIN
ERROR REFERENCE
AMP
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C1
C2 R2
ZFB VOUT
ZIN
C3 R3
COMP
FB
-
+
ISL6531
REFERENCE
R1
FIGURE 8. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
Modulator Break Frequency Equations
FLC=
--------------------1---------------------
2π x LO x CO
FESR=
---------------------1---------------------
2π x ESR x CO
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ISL6531.PDF ] | |
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