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PDF ISL6523 Data sheet ( Hoja de datos )
| Número de pieza | ISL6523 | |
| Descripción | VRM8.5 Dual PWM and Dual Linear Power System Controller | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ISL6523 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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TM
Data Sheet
January 2002
ISL6523
FN9024.1
VRM8.5 Dual PWM and Dual Linear Power
System Controller
The ISL6523 provides the power control and protection for
four output voltages in high-performance microprocessor
and computer applications. The IC integrates two PWM
controllers and two linear controllers, as well as the
monitoring and protection functions into a 28-pin SOIC
package. One PWM controller regulates the microprocessor
core voltage with a synchronous-rectified buck converter.
The second PWM controller supplies the computer system’s
AGTL+ 1.2V bus power with a standard buck converter. The
linear controllers regulate power for the 1.5V AGP bus and
the 1.8V power for the chipset core voltage and/or cache
memory circuits.
The ISL6523 includes an Intel VRM8.5 compatible, TTL 5-
input digital-to-analog converter (DAC) that adjusts the
microprocessor core-targeted PWM output voltage from
1.050V to 1.825V in 25mV steps. The precision reference
and voltage-mode control provide ±1% static regulation. The
second PWM controller’s output provides a voltage level of
1.2V with ±3% accuracy. The linear regulators use external
N-channel MOSFETs or bipolar NPN pass transistors to
provide fixed output voltages of 1.5V ±3% (VOUT3) and 1.8V
±3% (VOUT4).
The ISL6523 monitors all the output voltages. A delayed-
rising VTT (standard buck output) Power Good signal is
issued before the core PWM starts to ramp up. Another
system Power Good signal is issued when the core is within
±10% of the DAC setting and all other outputs are above
their under- voltage levels. Additional built-in overvoltage
protection for the core output uses the lower MOSFET to
prevent output voltages above 115% of the DAC setting. The
PWM controllers’ overcurrent function monitors the output
current by using the voltage drop across the upper
MOSFET’s rDS(ON), eliminating the need for a current
sensing resistor.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
ISL6523CB
0 to 70 28 Ld SOIC
ISL6523EVAL1
Evaluation Board
PKG.
NO.
M28.3
Features
• Provides 4 Regulated Voltages
- Microprocessor Core, AGTL+ Bus, AGP Bus Power,
and North/South Bridge Core
• Drives N-Channel MOSFETs
• Linear Regulator Drives Compatible with both MOSFET
and Bipolar Series Pass Transistors
• Simple Single-Loop Control Designs
- Voltage-Mode PWM Control
• Fast PWM Converter Transient Response
- High-Bandwidth Error Amplifiers
- Full 0% to 100% Duty Ratios
• Excellent Output Voltage Regulation
- Core PWM Output . . . . . . . . . . ±1% Over Temperature
- All Other Outputs . . . . . . . . . . . . . ±3% Over Temperature
• VRM8.5 TTL-Compatible 5-Bit DAC Microprocessor Core
Output Voltage Selection
- Wide Range . . . . . . . . . . . . . . . . . . . . 1.050V to 1.825V
• Power-Good Output Voltage Monitors
- Separate delayed VTT Power Good
• Overcurrent Fault Monitors
- Switching Regulators Do Not Require Extra Current
Sensing Elements, Use MOSFET’s rDS(ON)
• Small Converter Size
- Constant Frequency Operation
- 200kHz Internal Oscillator
Applications
• Motherboard Power Regulation for Computers
Pinout
ISL6523 (SOIC)
TOP VIEW
UGATE2 1
28 VCC
PHASE2 2
VID3 3
VID2 4
27 UGATE1
26 PHASE1
25 LGATE1
VID1 5
VID0 6
VID25 7
24 PGND
23 OCSET1
22 VSEN1
PGOOD 8
21 FB1
VTTPG 9
OCSET2 10
20 COMP1
19 VSEN3
VSEN2 11
18 DRIVE3
SS24 12
17 GND
SS13 13
16 VAUX
VSEN4 14
15 DRIVE4
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1 page  
ISL6523
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 (Continued)
PARAMETER
UGATE1,2 Sink
LGATE Source
LGATE Sink
PROTECTION
SYMBOL
RUGATE
ILGATE
RLGATE
TEST CONDITIONS
VGATE-PHASE = 1V
VCC = 12V, VLGATE1 = 1V
VLGATE = 1V
MIN TYP MAX UNITS
- 1.7 3.5
Ω
-1-
A
- 1.4 3.0
Ω
OCSET1,2 Current Source
Soft-Start Current
POWER GOOD
IOCSET
ISS13,24
VOCSET = 4.5VDC
VSS13,24 = 2.0VDC
170 200 230
- 28 -
µA
µA
VSEN1 Upper Threshold
(VSEN1/DACOUT)
VSEN1 Rising
108 - 110
%
VSEN1 Under-Voltage
(VSEN1/DACOUT)
VSEN1 Rising
92 - 94
%
VSEN1 Hysteresis (VSEN1/DACOUT)
PGOOD Voltage Low
VSEN2 Under-Voltage
VPGOOD
VSEN1 Falling
IPGOOD = -4mA
VSEN2 Rising
-2-
- - 0.8
1.00
%
V
V
VSEN2 Hysteresis
VSEN2 Falling
- 60 -
mV
VTTPG Voltage Low
NOTE:
2. Guaranteed by design
VVTTPG IVTTPG = -4mA
- - 0.8 V
Typical Performance Curve
140
CUGATE1 = CUGATE2 = CLGATE1 = C
120 VIN = 5V
VCC = 12V
100
C = 4800pF
80
C = 3600pF
60
C = 1500pF
40
20 C = 660pF
0
100 200 300 400 500 600 700 800 900 1000
SWITCHING FREQUENCY (kHz)
FIGURE 4. BIAS SUPPLY CURRENT vs FREQUENCY
Functional Pin Descriptions
VCC (Pin 28)
Provide a 12V bias supply for the IC to this pin. This pin also
provides the gate bias charge for all the MOSFETs
controlled by the IC. The voltage at this pin is monitored for
Power-On Reset (POR) purposes.
GND (Pin 17)
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
PGND (Pin 24)
This is the power ground connection. Tie the synchronous
PWM converter’s lower MOSFET source to this pin.
VAUX (Pin 16)
Connect this pin to the ATX 3.3V output. The voltage present
at this pin is monitored for sequencing purposes. This pin
provides the necessary base bias for the NPN pass
transistors, as well as the current sunk through the 5kΩ VID
pull-up resistors.
SS13 (Pin 13)
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 28µA current source, sets the
soft-start interval of the synchronous switching converter
(VOUT1) and the AGP regulator (VOUT3). A VTTPG high
signal is also delayed by the time interval required by the
charging of this capacitor from 0V to 1.25V (see Soft-Start
details).
SS24 (Pin 12)
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 28µA current source, sets the
soft-start interval of the standard buck converter. Pulling this
pin below 0.8V induces a chip reset (POR) and shutdown.
VTTPG (Pin 9)
VTTPG is an open collector output used to indicate the
status of the standard buck regulator output voltage. This pin
is pulled low when the output is below the under-voltage
threshold or when the SS13 pin is below 1.25V.
5
5 Page 
ISL6523
Figure 10 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level. The
reference voltage level is the DAC output voltage (DACOUT)
for PWM1. The error amplifier output (VE/A) is compared with
the oscillator (OSC) triangular wave to provide a pulse-width
modulated wave with an amplitude of VIN at the PHASE node.
The PWM wave is smoothed by the output filter (LO and CO)..
OSC
VIN
DRIVER
∆ VOSC
PWM
COMP
-
+
DRIVER
LO VOUT
PHASE
CO
VE/A
ZFB
-
+
ERROR
AMP
ZIN
REFERENCE
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C2
C1 R2
ZFB VOUT
ZIN
C3 R3
COMP
FB
-
+
ISL6523
DACOUT
R1
FIGURE 10. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A. This function is dominated by a DC
Gain, given by VIN/VOSC, and shaped by the output filter, with
a double pole break frequency at FLC and a zero at FESR.
Modulator Break Frequency Equations
FLC=
-------------------1--------------------
2π × LO × CO
FESR= 2----π-----×-----E----S--1---R------×-----C----O--
The compensation network consists of the error amplifier
(internal to the ISL6523) and the impedance networks ZIN and
ZFB. The goal of the compensation network is to provide a
closed loop transfer function with high 0dB crossing frequency
(f0dB) and adequate phase margin. Phase margin is the
difference between the closed loop phase at f0dB and 180o.
The equations below relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 10. Use these guidelines for locating the poles
and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1STZero Below Filter’s Double Pole (~75% FLC)
3. Place 2ND Zero at Filter’s Double Pole
4. Place 1ST Pole at the ESR Zero
5. Place 2ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Compensation Break Frequency Equations
FZ1 = 2----π-----×-----R---1--2-----×-----C----1--
FP1
=
---------------------------1---------------------------
2
π
×
R2
×
CC-----11-----×+-----CC-----22-
FZ2 = 2----π-----×-----(---R----1-----+-1----R-----3---)----×-----C-----3-
FP2 = 2----π-----×-----R---1--3-----×----C-----3--
Figure 11 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown in Figure 11. Using the above guidelines
should yield a Compensation Gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at FP2 with the capabilities
of the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 11 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the compensation
transfer function and plotting the gain.
100
FZ1
FZ2 FP1 FP2
OPEN LOOP
ERROR AMP GAIN
80
20
log
V----V-P---I--–-N----P--
60
40 COMPENSATION
GAIN
20
0
-20
20log
RR-----21--
MODULATOR
-40
GAIN
FLC FESR
CLOSED LOOP
GAIN
-60
10 100 1K 10K 100K 1M 10M
FREQUENCY (Hz)
FIGURE 11. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW)
overall loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than
45 degrees. Include worst case component variations when
determining phase margin.
PWM2 Controller Feedback Compensation
To reduce the number of external small-signal components
required by a typical application, the standard PWM
controller is internally stabilized. The only stability criteria
that needs to be met relates the minimum value of the output
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ISL6523.PDF ] | |
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