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ISL6520B の電気的特性と機能

ISL6520BのメーカーはIntersil Corporationです、この部品の機能は「Single Synchronous Buck Pulse-Width Modulation (PWM) Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL6520B
部品説明 Single Synchronous Buck Pulse-Width Modulation (PWM) Controller
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ISL6520B Datasheet, ISL6520B PDF,ピン配置, 機能
®
Data Sheet
April 2003
ISL6520B
FN9083.1
Single Synchronous Buck Pulse-Width
Modulation (PWM) Controller
The ISL6520B makes simple work out of implementing a
complete control scheme for a DC-DC stepdown converter.
Designed to drive N-channel MOSFETs in a synchronous
buck topology, the ISL6520B integrates the control, output
adjustment and monitoring functions into a single 8-Lead
package.
The ISL6520B provides simple, single feedback loop,
voltage-mode control with fast transient response. The
output voltage can be precisely regulated to as low as 0.8V,
with a maximum tolerance of ±1.5% over temperature and
line voltage variations. A fixed frequency oscillator reduces
design complexity, while balancing typical application cost
and efficiency.
The error amplifier features a 15MHz gain-bandwidth
product and 8V/µs slew rate which enables high converter
bandwidth for fast transient performance. The resulting
PWM duty cycles range from 0% to 100%.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
PKG.
NO.
ISL6520BCB
0 to 70 8 Ld SOIC
M8.15
ISL6520BIB
-40 to 85 8 Ld SOIC
M8.15
ISL6520BCR
0 to 70 16 Ld 4x4mm QFN L16.4x4
ISL6520BIR
-40 to 85 16 Ld 4x4mm QFN L16.4x4
ISL6520EVAL1 Evaluation Board
Pinouts
ISL6520B (8 LD SOIC)
TOP VIEW
BOOT 1
UGATE 2
GND 3
LGATE 4
8 PHASE
7 COMP/SD
6 FB
5 VCC
ISL6520B (16 LD QFN)
TOP VIEW
16 15 14 13
BOOT 1
12 NC
UGATE 2
GND 3
GND
11 COMP/SD
10 NC
NC 4
9 FB
5678
Features
• Operates from +5V Input
• 0.8V to VIN Output Range
- 0.8V Internal Reference
- ±1.5% Over Line Voltage and Temperature
• Drives N-Channel MOSFETs
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Cycle
• Small Converter Size
- 300kHz Fixed Frequency Oscillator
- Internal Soft Start
- 8 Ld SOIC or 16Ld 4x4mm QFN
• QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
Applications
• Power Supplies for Microprocessors
- PCs
- Embedded Controllers
• Subsystem Power Supplies
- PCI/AGP/GTL+ Buses
- ACPI Power Control
- SSTL-2 and DDR SDRAM Bus Termination Supply
• Cable Modems, Set Top Boxes, and DSL Modems
• DSP and Core Communications Processor Supplies
• Memory Supplies
• Personal Computer Peripherals
• Industrial Power Supplies
• 5V-Input DC-DC Regulators
• Low-Voltage Distributed Power Supplies
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL6520B pdf, ピン配列
ISL6520B
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
Absolute Boot Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . +15.0V
Upper Driver Supply Voltage, VBOOT - VPHASE . . . . . . . . . . . +6.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
Ambient Temperature Range - ISL6520BC . . . . . . . . . . 0oC to 70oC
Ambient Temperature Range - ISL6520BI . . . . . . . . . -40oC to 85oC
Junction Temperature Range . . . . . . . . . . . . . . . . . -40oC to 125oC
Thermal Information
Thermal Resistance
θJA (oC/W) θJC (oC/W)
SOIC Package (Note 1) . . . . . . . . . . . . . . 95
N/A
QFN Package (Note 2, 3). . . . . . . . . . . . . . 45
7
Maximum Junction Temperature
(Plastic Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . -65oC to 150oC
Maximum Lead Temperature
(Soldering 10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
VCC SUPPLY CURRENT
Nominal Supply
POWER-ON RESET
IVCC
2.6 3.2 3.8
mA
Rising VCC POR Threshold
POR
4.19 4.30 4.50
V
VCC POR Threshold Hysteresis
- 0.25 -
V
OSCILLATOR
Frequency
fOSC
ISL6520BC, VCC = 5V
ISL6520BI, VCC = 5V
250 300 340
230 300 340
kHz
kHz
Ramp Amplitude
REFERENCE
VOSC
- 1.5 - VP-P
Reference Voltage Tolerance
ISL6520BC
-1.5 - +1.5 %
ISL6520BI
-2.5 +2.5 %
Nominal Reference Voltage
ERROR AMPLIFIER
VREF
- 0.800 -
V
DC Gain
Guaranteed By Design
- 88 -
dB
Gain-Bandwidth Product
GBWP
- 15 - MHz
Slew Rate
SR
- 8 - V/µs
GATE DRIVERS
Upper Gate Source Current
Upper Gate Sink Current
Lower Gate Source Current
Lower Gate Sink Current
DISABLE
IUGATE-
SRC
VBOOT - VPHASE = 5V, VUGATE = 4V
IUGATE-SNK
ILGATE-SRC VVCC = 5V, VLGATE = 4V
ILGATE-SNK
- -1 -
-1-
- -1 -
-2-
A
A
A
A
Disable Threshold
VDISABLE
- 0.8 -
V
3


3Pages


ISL6520B 電子部品, 半導体
ISL6520B
Gain and the output filter (LO and CO), with a double pole
break frequency at FLC and a zero at FESR. The DC Gain of
the modulator is simply the input voltage (VIN) divided by the
peak-to-peak oscillator voltage VOSC.
Modulator Break Frequency Equations
FLC=
---------------------1---------------------
2π x LO x CO
FESR= 2----π------x-----E----S--1---R------x-----C-----O---
The compensation network consists of the error amplifier
(internal to the ISL6520B) and the impedance networks ZIN
and ZFB. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f0dB and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 4. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth.
2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC).
3. Place 2ND Zero at Filter’s Double Pole.
4. Place 1ST Pole at the ESR Zero.
5. Place 2ND Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
FZ1 = -2---π------x-----R--1--2------x-----C----1-
FZ2 = 2----π------x-----(--R-----1----+-1----R-----3---)----x-----C-----3-
FP1
=
---------------------------1-----------------------------
2π
x
R2
x
C-C----11-----+x-----CC----2-2-
FP2 = -2---π------x-----R--1--3------x-----C----3-
Figure 5 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 5. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at FP2 with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 5 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW)
overall loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
100 FZ1 FZ2 FP1 FP2
80
OPEN LOOP
60 ERROR AMP GAIN
40
20LOG
20 (R2/R1)
20LOG
0 (VIN/VOSC)
MODULATOR
-20 GAIN
-40
FLC FESR
-60
10 100 1K 10K 100K
COMPENSATION
GAIN
CLOSED LOOP
GAIN
1M 10M
FREQUENCY (Hz)
FIGURE 5. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern components and loads are capable of producing
transient load rates above 1A/ns. High frequency capacitors
initially supply the transient and slow the current load rate
seen by the bulk capacitors. The bulk filter capacitor values
are generally determined by the ESR (Effective Series
Resistance) and voltage rating requirements rather than
actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
6

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部品番号部品説明メーカ
ISL6520

Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

Intersil Corporation
Intersil Corporation
ISL6520A

Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

Intersil Corporation
Intersil Corporation
ISL6520B

Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

Intersil Corporation
Intersil Corporation


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