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PDF ISL6520A Data sheet ( Hoja de datos )
| Número de pieza | ISL6520A | |
| Descripción | Single Synchronous Buck Pulse-Width Modulation (PWM) Controller | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
March 2003
ISL6520A
FN9016.1
Single Synchronous Buck Pulse-Width
Modulation (PWM) Controller
The ISL6520A makes simple work out of implementing a
complete control and protection scheme for a DC-DC
stepdown converter. Designed to drive N-channel MOSFETs
in a synchronous buck topology, the ISL6520A integrates
the control, output adjustment, monitoring and protection
functions into a single 8-Lead package.
The ISL6520A provides simple, single feedback loop,
voltage-mode control with fast transient response. The
output voltage can be precisely regulated to as low as 0.8V,
with a maximum tolerance of ±1.5% over temperature and
line voltage variations. A fixed frequency oscillator reduces
design complexity, while balancing typical application cost
and efficiency.
The error amplifier features a 15MHz gain-bandwidth
product and 8V/µs slew rate which enables high converter
bandwidth for fast transient performance. The resulting
PWM duty cycles range from 0% to 100%.
Protection from overcurrent conditions is provided by
monitoring the rDS(ON) of the upper MOSFET to inhibit PWM
operation appropriately. This approach simplifies the
implementation and improves efficiency by eliminating the
need for a current sense resistor.
Ordering Information
PART NUMBER
ISL6520ACB
TEMP.
RANGE (oC)
PACKAGE
0 to 70 8 Ld SOIC
PKG.
NO.
M8.15
ISL6520AIB
ISL6520ACR
ISL6520AIR
ISL6520EVAL1
-40 to 85 8 Ld SOIC
M8.15
0 to 70 16 Ld 4x4mm QFN L16.4x4
-40 to 85 16 Ld 4x4mm QFN L16.4x4
Evaluation Board
Features
• Operates from +5V Input
• 0.8V to VIN Output Range
- 0.8V Internal Reference
- ±1.5% Over Line Voltage and Temperature
• Drives N-Channel MOSFETs
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Cycle
• Lossless, Programmable Overcurrent Protection
- Uses Upper MOSFET’s rDS(on)
• Small Converter Size
- 300kHz Fixed Frequency Oscillator
- Internal Soft Start
- 8 Ld SOIC or 16Ld 4x4mm QFN
• QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
Applications
• Power Supplies for Microprocessors
- PCs
- Embedded Controllers
• Subsystem Power Supplies
- PCI/AGP/GTL+ Buses
- ACPI Power Control
- SSTL-2 and DDR SDRAM Bus Termination Supply
• Cable Modems, Set Top Boxes, and DSL Modems
• DSP and Core Communications Processor Supplies
• Memory Supplies
• Personal Computer Peripherals
• Industrial Power Supplies
• 5V-Input DC-DC Regulators
• Low-Voltage Distributed Power Supplies
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
OUTPUT INDUCTOR
CURRENT
5A/DIV.
ISL6520A
method provides a rapid and controlled output voltage rise. The
entire startup sequence typically take about 11ms.
COMP/OCSET
1V/DIV.
VOUT
500mV/DIV.
TIME (5ms/DIV.)
FIGURE 1. OVERCURRENT OPERATION
The overcurrent function will trip at a peak inductor current
(IPEAK) determined by:
IPEAK = I--O-----C----S----E-r--D-T---S--x--(--O-R----N-O---)-C-----S----E---T--
where IOCSET is the internal OCSET current source (20µA
typical). The OC trip point varies mainly due to the
MOSFET’s rDS(ON) variations. To avoid overcurrent tripping
in the normal operating load range, find the ROCSET resistor
from the equation above with:
1. The maximum rDS(ON) at the highest junction
temperature.
2.
3.
The minimum IOCSET
Determine IPEAK for
where ∆I is the output
from the specification table.
IPEAK
>
IOUT(MAX)
+
(---∆----I---)
2
,
inductor ripple current.
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
Soft Start
The POR function initiates the soft start sequence after the
overcurrent set point has been sampled. Soft start clamps the
error amplifier output (COMP pin) and reference input (non-
inverting terminal of the error amp) to the internally generated
Soft Start voltage. Figure 2 shows a typical start up interval
where the COMP/OCSET pin has been released from a
grounded (system shutdown) state. Initially, the COMP/OCSET
is used to sample the overcurrent setpoint by disabling the error
amplifier and drawing 20µA through ROCSET. Once the
overcurrent level has been sampled, the soft start function is
initiated. The clamp on the error amplifier (COMP/OCSET pin)
initially controls the converter’s output voltage during soft start.
The oscillator’s triangular waveform is compared to the ramping
error amplifier voltage. This generates PHASE pulses of
increasing width that charge the output capacitor(s). When the
internally generated Soft Start voltage exceeds the feedback
(FB pin) voltage, the output voltage is in regulation. This
TIME (2ms/DIV.)
FIGURE 2. SOFT START INTERVAL
Current Sinking
The ISL6520A incorporates a MOSFET shoot-through
protection method which allows a converter to sink current
as well as source current. Care should be exercised when
designing a converter with the ISL6520A when it is known
that the converter may sink current.
When the converter is sinking current, it is behaving as a
boost converter that is regulating it’s input voltage. This
means that the converter is boosting current into the VCC
rail, which supplies the bias voltage to the ISL6520A. If there
is nowhere for this current to go, such as to other distributed
loads on the VCC rail, through a voltage limiting protection
device, or other methods, the capacitance on the VCC bus
will absorb the current. This situation will allow voltage level
of the VCC rail to increase. If the voltage level of the rail is
boosted to a level that exceeds the maximum voltage rating
of the ISL6520A, then the IC will experience an irreversible
failure and the converter will no longer be operational.
Ensuring that there is a path for the current to follow other
than the capacitance on the rail will prevent this failure
mode.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.
5
5 Page 
ISL6520A
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A 0.80 0.90 1.00 -
A1 -
- 0.05 -
A2 -
- 1.00 9
A3 0.20 REF 9
b 0.23 0.28 0.38 5, 8
D
4.00 BSC
-
D1 3.75 BSC 9
D2 1.95 2.10 2.25 7, 8
E
4.00 BSC
-
E1 3.75 BSC 9
E2 1.95 2.10 2.25 7, 8
e
0.65 BSC
-
k 0.25
-
--
L 0.35 0.60 0.75 8
L1 -
- 0.15 10
N 16 2
Nd 4 3
Ne 4 3
P-
- 0.60 9
θ-
- 12 9
Rev. 4 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet ISL6520A.PDF ] | |
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