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ISL6505EVAL1 の電気的特性と機能

ISL6505EVAL1のメーカーはIntersil Corporationです、この部品の機能は「Multiple Linear Power Controller with ACPI Control Interface」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL6505EVAL1
部品説明 Multiple Linear Power Controller with ACPI Control Interface
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ISL6505EVAL1 Datasheet, ISL6505EVAL1 PDF,ピン配置, 機能
®
Data Sheet
November 2003
ISL6505
FN9109.1
Multiple Linear Power Controller with
ACPI Control Interface
The ISL6505 complements other power building blocks
(voltage regulators) in ACPI-compliant designs for
microprocessor and computer applications. The IC
integrates three linear controllers/regulators, switching,
monitoring and control functions into a 20-pin wide-body
SOIC or 20-pin QFN (also known as MLF) 5x5 package.
The ISL6505’s operating mode (active or sleep outputs) is
selectable through two digital control pins, S3 and S5.
One linear controller generates the 3.3VDUAL/3.3VSB
voltage plane from the ATX supply’s 5VSB output, powering
the south bridge and the PCI slots through an external NPN
pass transistor during sleep states (S3, S4/S5). In active
state (during S0 and S1/S2), the 3.3VDUAL/3.3VSB linear
regulator uses an external N-channel pass MOSFET to
connect the outputs directly to the 3.3V input supplied by an
ATX power supply, for minimal losses. The
3.3VDUAL/3.3VSB output is active for as long as the ATX 5VSB
voltage is applied to the chip.
A controller powers up the 5VDUAL plane by switching in the
ATX 5V output through an NMOS transistor in active states,
or by switching in the ATX 5VSB through a PMOS (or PNP)
transistor in S3 sleep state. In S4/S5 sleep states, the
ISL6505 5VDUAL output is either shut down or stays on,
based on the state of the EN5 pin.
An internal linear regulator supplies the 1.2V for the voltage
identification circuitry (VID) only during active states (S0 and
S1/S2), and uses the 3V3 pin as input source for its internal
pass element.
A linear controller generates VOUT1 from the
3.3VDUAL/3.3VSB voltage plane, using an external NFET.
The voltage is user-programmable to values between 1.2V
and 1.5V, using an external resistor divider. The mode is
user-selectable with the LAN pin; a logic high (or open)
selects the 10/100 LAN mode, where VOUT1 is always on
(S0-S5); a logic low selects the Gigabit Ethernet mode,
where VOUT1 is only on during active modes (S0-S2).
Ordering Information
Features
• Provides four ACPI-Controlled Voltages
- 5VDUAL USB/Keyboard/Mouse
- 3.3VDUAL/3.3VSB PCI/Auxiliary/LAN
- 1.2VVID Processor VID Circuitry
- VOUT1 (1.2V - 1.5V programmable) LAN/Ethernet
• Excellent Output Voltage Regulation
- All Outputs: ±2.0% over temperature (as applicable)
• Small Size; Very Low External Component Count
• Undervoltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
Applications
ACPI-Compliant Power Regulation for Motherboards
Pinouts
ISL6505 (20-LEAD-WIDE SOIC) TOP VIEW
FB1 1
DR1 2
3V3DLSB 3
3V3DL 4
1V2VID 5
3V3 6
5V 7
EN5 8
S3 9
S5 10
20 5VSB
19 VID_CT
18 VID_PG
17 SS
16 LAN
15 5VDL
14 5VDLSB
13 DLA
12 FAULT
11 GND
ISL6505 (5 X 5 QFN) TOP VIEW
20 19 18 17 16
3V3DL 1
1V2VID 2
15 VID_PG
14 SS
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
PKG.
DWG. #
ISL6505CB
0 to 70 20 Ld Wide SOIC M20.3
ISL6505CR
0 to 70 20 Ld 5x5 QFN L20.5x5
ISL6505EVAL1
Evaluation Board (SOIC)
ISL6505AEVAL2 Evaluation Board (QFN)
3V3 3
5V 4
EN5 5
13 LAN
12 5VDL
11 5VDLSB
6 7 8 9 10
NOTE: The QFN bottom pad is electrically connected to the IC substrate, at GND potential.
It can be left unconnected, or connected to GND; do NOT connect to another potential.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL6505EVAL1 pdf, ピン配列
Simplified Power System Diagram
+5VIN
+12VIN
+5VSB
+3.3VIN
ISL6505
FAULT
Q2
3.3VDUAL /3.3VSB
3.3V
VOUT1
Q3
Q6
R20
SHUTDOWN
SX, EN5, LAN
R21
4
Typical Application
+5VIN
+12VIN
+5VSB
+3.3VIN
ISL6505
LINEAR
CONTROLLER
LINEAR
REGULATOR
LINEAR
CONTROLLER
CONTROL
LOGIC
FIGURE 2.
1.2VVID
1.2V
VID_PG
Q4
Q5
5VDUAL
5V
VOUT1
1.2V - 1.5V
COUT1
Q2
RDLA
Q6
DR1
R20
FB1
R21
3V3DLSB
VOUT3
3.3VDUAL/3.3VSB
FAULT
SLP_S3
SLP_S5
SHUTDOWN
Q3
COUT3
EN5
LAN
3V3DL
EN5
LAN
FAULT
S3
S5
SS
CSS
3V3 5V 5VSB
1V2VID
VID_CT
CCT_VID
COUT2
VOUT2
1.2VVID
ISL6505
VID_PG
5VDLSB
DLA
5VDL
Q5
COUT4
VID PGOOD
Q4
VOUT4
5VDUAL
GND
FIGURE 3.
3


3Pages


ISL6505EVAL1 電子部品, 半導体
ISL6505
Functional Pin Description (Pin numbers
for SOIC and QFN)
3V3 (Pin 6 SOIC; Pin 3 QFN)
Connect this pin to the ATX 3.3V output. This pin provides
the output current for the 1V2VID pin, and is monitored for
power quality.
5V (Pin 7 SOIC; Pin 4 QFN)
Connect this pin to the ATX 5V output. This pin is only
monitored for power quality.
5VSB (Pin 20 SOIC; Pin 17 QFN)
Provide a very well de-coupled 5V bias supply for the IC to
this pin by connecting it to the ATX 5VSB output. This pin
provides all the chip’s bias as well as the base current for Q2
(see typical application diagram). The voltage at this pin is
monitored for power-on reset (POR) purposes.
GND (Pin 11 SOIC; Pin 8 QFN)
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
S3 and S5 (Pins 9, 10 SOIC; Pins 6, 7 QFN)
These pins switch the IC’s operating state from active (S0,
S1/S2) to S3 and S4/S5 sleep states. These are digital
inputs featuring internal 50µA (typical) current source pull-
ups to 5VSB. Internal circuitry de-glitches these pins for
disturbances lasting as long as 2µs (typically). Additional
circuitry blocks illegal state transitions (such as S4/S5 to S3),
but does allow S3 to S4/S5. Connect S3 and S5
respectively to the computer system’s SLP_S3 and SLP_S5
signals.
EN5 (Pin 8 SOIC; Pin 5 QFN)
This digital input selects whether the 5VDL output stays up
or shuts down during the S5 Sleep Mode. It has a 10µA
typical pull-up current source. A logic high (5V) or open will
keep the 5VDL on during S5; a logic low (GND) will shut it off
during S5. NOTE: This pin should be tied low or high (or
open) on the board; it was not designed to be changed
during normal operation.
LAN (Pin 16 SOIC; Pin 13 QFN)
This digital input selects between two modes for the VOUT1
regulator. It has a 10µA pull-up current source. A logic high
(5V) or open selects the 10/100 LAN mode, where VOUT1
stays on all of the time (active and sleep modes). A logic low
(GND) selects the Gigabit Ethernet mode, where VOUT1 is
only on during active (S0, S1) modes. Note that this
selection is independent of the voltage selection of VOUT1
(which is determined by the external resistor divider). NOTE:
This pin should be tied low or high (or open) on the board; it
was not designed to be changed during normal operation.
FAULT (Pin 12 SOIC; Pin 9 QFN)
This digital output pin is used to report the fault condition by
being pulled to 5VSB (pulled to GND if no fault). It is a
CMOS digital output; an external pull-down resistor is NOT
required. In case of an undervoltage on any of the controlled
outputs, on any of the monitored ATX voltages (3V3 or 5V;
not 12V), or in case of an overtemperature event, this pin is
used to report the fault condition.
SS (Pin 17 SOIC; Pin 14 QFN)
Connect this pin to a small ceramic capacitor (no less than
5nF; 0.1µF recommended). The internal soft-start (SS)
current source along with the external capacitor creates a
voltage ramp used to control the ramp-up of the output
voltages. Pulling this pin low (to GND) with an open-drain
device shuts down all the outputs as well as forces the
FAULT pin low. The CSS capacitor is also used to provide a
controlled voltage slew rate during active-to-sleep transitions
on the 3.3VDUAL/3.3VSB output.
3V3DL (Pin 4 SOIC; Pin 1 QFN)
Connect this pin to the 3.3V dual/stand-by output (VOUT3).
In sleep states, the voltage at this pin is regulated to 3.3V; in
active states, ATX 3.3V output is delivered to this node
through a fully-on NFET transistor. During all operating
states, this pin is monitored for undervoltage events. This pin
provides all the output current delivered by VOUT1.
3V3DLSB (Pin 3 SOIC; Pin 20 QFN)
Connect this pin to the base of a suitable NPN transistor. In
sleep state, this transistor is used to regulate the voltage at
the 3V3DL pin to 3.3V.
DLA (Pin 13 SOIC; Pin 10 QFN)
This pin is an open-collector output. Connect a 1kresistor
from this pin to the ATX 12V output. This resistor is used to
pull the gates of suitable NFETs to 12V, which in active
state, switch in the ATX 3.3V and 5V outputs into the
3.3VDUAL/3.3VSB and 5VDUAL outputs, respectively.
5VDL (Pin 15 SOIC; Pin 12 QFN)
Connect this pin to the 5VDUAL output (VOUT4). In either
operating state (when on), the voltage at this pin is provided
through a fully-on MOSFET transistor. This pin is also
monitored for undervoltage events.
5VDLSB (Pin 14 SOIC; Pin 11 QFN)
Connect this pin to the gate of a suitable PFET or bipolar
PNP. This transistor is switched on, connecting the ATX
5VSB output to the 5VDUAL regulator output during S3, and
if EN5 is open or high, during S5. If EN5 is low (GND), the
transistor is switched off in S5.
DR1 (Pin 2 SOIC; Pin 19 QFN)
This output pin drives the gate of an external NFET
transistor to create VOUT1, which draws its output current
from the 3V3DL pin.
6

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部品番号部品説明メーカ
ISL6505EVAL1

Multiple Linear Power Controller with ACPI Control Interface

Intersil Corporation
Intersil Corporation


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