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ISL6504A の電気的特性と機能

ISL6504AのメーカーはIntersil Corporationです、この部品の機能は「Multiple Linear Power Controller with ACPI Control Interface」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL6504A
部品説明 Multiple Linear Power Controller with ACPI Control Interface
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ISL6504A Datasheet, ISL6504A PDF,ピン配置, 機能
®
Data Sheet
ISL6504, ISL6504A
July 2003
FN9062.1
Multiple Linear Power Controller with
ACPI Control Interface
The ISL6504 and ISL6504A complement other power
building blocks (voltage regulators) in ACPI-compliant
designs for microprocessor and computer applications. The
IC integrates three linear controllers/regulators, switching,
monitoring and control functions into a 16-pin wide-body
SOIC or 20-pin QFN 6x6 package. The ISL6504, ISL6504A
operating mode (active outputs or sleep outputs) is
selectable through two digital control pins, S3 and S5.
One linear controller generates the 3.3VDUAL/3.3VSB
voltage plane from the ATX supply’s 5VSB output, powering
the south bridge and the PCI slots through an external NPN
pass transistor during sleep states (S3, S4/S5). In active
state (during S0 and S1/S2), the 3.3VDUAL/3.3VSB linear
regulator uses an external N-channel pass MOSFET to
connect the outputs directly to the 3.3V input supplied by an
ATX power supply, for minimal losses.
A controller powers up the 5VDUAL plane by switching in the
ATX 5V output through an NMOS transistor in active states,
or by switching in the ATX 5VSB through a PMOS (or PNP)
transistor in S3 sleep state. In S4/S5 sleep states, the
ISL6504 5VDUAL output is shut down. In the ISL6504A, the
5VDUAL output stays on during S4/S5 sleep states. This is
the only difference between the two parts; see Table 1.
An internal linear regulator supplies the 1.2V for the voltage
identification circuitry (VID) only during active states (S0 and
S1/S2), and uses the 3V3 pin as input source for its internal
pass element. Another internal regulator outputs a 1.5VSB
chip-set standby supply, which uses the 3V3DL pin as input
source for its internal pass element. The 3.3VDUAL/3.3VSB
and 1.5VSB outputs are active for as long as the ATX 5VSB
voltage is applied to the chip.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
PKG.
DWG. #
ISL6504CB
0 to 70 16 Ld Wide SOIC M16.3
ISL6504CR
0 to 70 20 Ld QFN
L20.6x6
ISL6504EVAL1 Evaluation Board
ISL6504ACB
0 to 70 16 Ld Wide SOIC M16.3
ISL6504ACR
0 to 70 20 Ld QFN
L20.6x6
ISL6504AEVAL1 Evaluation Board
Coming soon
0 to 70 16 Ld Narrow SOIC M16.15
Features
• Provides four ACPI-Controlled Voltages
- 5VDUAL USB/Keyboard/Mouse
- 3.3VDUAL/3.3VSB PCI/Auxiliary/LAN
- 1.2VVID Processor VID Circuitry
- 1.5VSB ICH4 Resume Well
• Excellent Output Voltage Regulation
- All Outputs: ±2.0% over temperature (as applicable)
• Small Size; Very Low External Component Count
• Undervoltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
• QFN Package:
- Near Chip Scale Package Footprint; Improved PCB
Efficiency; Thinner profile
Applications
ACPI-Compliant Power Regulation for Motherboards
- ISL6504: 5VDUAL is shut down in S4/S5 sleep states
- ISL6504A: 5VDUAL stays on in S4/S5 sleep states
Pinouts
ISL6504/A (WIDE BODY SOIC)
TOP VIEW
1V5SB 1
3V3DLSB 2
3V3DL 3
1V2VID 4
3V3 5
S3 6
S5 7
GND 8
16 5VSB
15 VID_CT
14 VID_PG
13 SS
12 5VDL
11 5VDLSB
10 DLA
9 FAULT
NOTE: SOIC layout should accomodate both wide and narrow footprints.
ISL6504/A (6 X 6 QFN)
TOP VIEW
3V3DL 1
NC 2
1V2VID 3
3V3 4
S3 5
20 19 18 17 16
15 VID_PG
14 SS
13 NC
12 5VDL
11 5VDLSB
6 7 8 9 10
NOTE: The QFN bottom pad is electrically connected to the IC substrate, at
GND potential. It can be left unconnected, or connected to GND; do NOT
connect to another potential.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL6504A pdf, ピン配列
ISL6504, ISL6504A
Simplified Power System Diagram
+5VIN
+12VIN
+5VSB
+3.3VIN
1.5VSB
1.5V
Q2
3.3VDUAL /3.3VSB
3.3V
FAULT
Q3
LINEAR
REGULATOR
LINEAR
CONTROLLER
LINEAR
REGULATOR
ISL6504/A
CONTROL
LOGIC
SHUTDOWN
SX
2
FIGURE 2.
1.2VVID
1.2V
VID_PG
Q4
Q5
5VDUAL
5V
Typical Application
+5VIN
+12VIN
+5VSB
+3.3VIN
VOUT1
1.5VSB
COUT1
Q1
VOUT3
3.3VDUAL/3.3VSB
FAULT
SLP_S3
SLP_S5
Q2
COUT3
SHUTDOWN
3
1V5SB
RDLA
3V3DLSB
3V3DL
FAULT
S3
S5
SS
CSS
3V3 5VSB
1V2VID
VID_CT
CCT_VID
COUT2
VOUT2
1.2VVID
ISL6504/A
VID_PG
5VDLSB
DLA
5VDL
Q4
COUT4
VID PGOOD
Q3
VOUT4
5VDUAL
GND
FIGURE 3.


3Pages


ISL6504A 電子部品, 半導体
ISL6504, ISL6504A
Functional Pin Description (SOIC pinout)
3V3 (Pin 5)
Connect this pin to the ATX 3.3V output. This pin provides
the output current for the 1V2VID pin, and is monitored for
power quality.
5VSB (Pin 16)
Provide a very well de-coupled 5V bias supply for the IC to
this pin by connecting it to the ATX 5VSB output. This pin
provides all the chip’s bias as well as the base current for Q2
(see typical application diagram). The voltage at this pin is
monitored for power-on reset (POR) purposes.
GND (Pin 8)
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
S3 and S5 (Pins 6 and 7)
These pins switch the IC’s operating state from active (S0,
S1/S2) to S3 and S4/S5 sleep states. These are digital
inputs featuring internal 50k(typical) resistor pull-ups to
5VSB. Internal circuitry de-glitches these pins for
disturbances lasting as long as 2µs (typically). Additional
circuitry blocks any illegal state transitions (such as S3 to
S4/S5 or vice versa). Respectively, connect S3 and S5 to
the computer system’s SLP_S3 and SLP_S5 signals.
FAULT (Pin 9)
In case of an undervoltage on any of the controlled outputs,
on any of the monitored ATX voltages, or in case of an
overtemperature event, this pin is used to report the fault
condition by being pulled to 5VSB. Connect a 1kresistor
from this pin to GND.
SS (Pin 13)
Connect this pin to a small ceramic capacitor (no less than
5nF; 0.1µF recommended). The internal soft-start (SS)
current source along with the external capacitor creates a
voltage ramp used to control the ramp-up of the output
voltages. Pulling this pin low with an open-drain device shuts
down all the outputs as well as force the FAULT pin low. The
CSS capacitor is also used to provide a controlled voltage
slew rate during active-to-sleep transitions on the
3.3VDUAL/3.3VSB output.
3V3DL (Pin 3)
Connect this pin to the 3.3V dual/stand-by output (VOUT3).
In sleep states, the voltage at this pin is regulated to 3.3V; in
active states, ATX 3.3V output is delivered to this node
through a fully-on N-MOS transistor. During all operating
states, this pin is monitored for undervoltage events. This pin
provides all the output current delivered by the 1V5SB pin.
3V3DLSB (Pin 2)
Connect this pin to the base of a suitable NPN transistor. In
sleep state, this transistor is used to regulate the voltage at
the 3V3DL pin to 3.3V.
DLA (Pin 10)
This pin is an open-collector output. Connect a 1kresistor
from this pin to the ATX 12V output. This resistor is used to
pull the gates of suitable N-MOSFETs to 12V, which in
active state, switch in the ATX 3.3V and 5V outputs into the
3.3VDUAL/3.3VSB and 5VDUAL outputs, respectively.
5VDL (Pin 12)
Connect this pin to the 5VDUAL output (VOUT4). In either
operating state (when on), the voltage at this pin is provided
through a fully-on MOS transistor. This pin is also monitored
for undervoltage events.
5VDLSB (Pin 11)
Connect this pin to the gate of a suitable P-MOSFET or
bipolar PNP. ISL6504: In S3 sleep state, this transistor is
switched on, connecting the ATX 5VSB output to the
5VDUAL regulator output. ISL6504A: In S3 and S4/S5 sleep
state, this transistor is switched on, connecting the ATX
5VSB output to the 5VDUAL regulator output.
1V5SB (Pin 1)
This pin is the output of the internal 1.5V regulator (VOUT1).
This internal regulator operates for as long as 5VSB is
applied to the IC and draws its output current from the
3V3DL pin. This pin is monitored for undervoltage events.
1V2VID (Pin 4)
This pin is the output of the internal 1.2V voltage
identification (VID) regulator (VOUT2). This internal regulator
operates only in active states (S0, S1/S2) and is shut off
during any sleep state. This regulator draws its output
current from the 3V3 pin. This pin is monitored for
undervoltage events.
VID_PG (Pin 14)
This pin is the open collector output of the 1V2VID power
good comparator. Connect a 10kpull-up resistor from this
pin to the 1V2VID output. As long as the 1V2VID output is
below its UV threshold, this pin is pulled low.
VID_CT (Pin 15)
Connect a small capacitor from this pin to ground. The
capacitor is used to delay the VID_PG reporting the 1V2VID
has reached power good limits.
Description
Operation
The ISL6504/A controls 4 output voltages (Refer to Figures
1, 2, and 3). It is designed for microprocessor computer
applications with 3.3V, 5V, 5VSB, and 12V bias input from an
ATX power supply. The IC is composed of three linear
controllers/regulators supplying the computer system’s
1.5VSB (VOUT1), 3.3VSB and PCI slots’ 3.3VAUX power
(VOUT3), the 1.2V VID circuitry power (VOUT2), a dual
switch controller supplying the 5VDUAL voltage (VOUT4), as
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部品番号部品説明メーカ
ISL6504

Multiple Linear Power Controller with ACPI Control Interface

Intersil Corporation
Intersil Corporation
ISL6504A

Multiple Linear Power Controller with ACPI Control Interface

Intersil Corporation
Intersil Corporation


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