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PDF ISL6504 Data sheet ( Hoja de datos )
| Número de pieza | ISL6504 | |
| Descripción | Multiple Linear Power Controller with ACPI Control Interface | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
ISL6504, ISL6504A
July 2003
FN9062.1
Multiple Linear Power Controller with
ACPI Control Interface
The ISL6504 and ISL6504A complement other power
building blocks (voltage regulators) in ACPI-compliant
designs for microprocessor and computer applications. The
IC integrates three linear controllers/regulators, switching,
monitoring and control functions into a 16-pin wide-body
SOIC or 20-pin QFN 6x6 package. The ISL6504, ISL6504A
operating mode (active outputs or sleep outputs) is
selectable through two digital control pins, S3 and S5.
One linear controller generates the 3.3VDUAL/3.3VSB
voltage plane from the ATX supply’s 5VSB output, powering
the south bridge and the PCI slots through an external NPN
pass transistor during sleep states (S3, S4/S5). In active
state (during S0 and S1/S2), the 3.3VDUAL/3.3VSB linear
regulator uses an external N-channel pass MOSFET to
connect the outputs directly to the 3.3V input supplied by an
ATX power supply, for minimal losses.
A controller powers up the 5VDUAL plane by switching in the
ATX 5V output through an NMOS transistor in active states,
or by switching in the ATX 5VSB through a PMOS (or PNP)
transistor in S3 sleep state. In S4/S5 sleep states, the
ISL6504 5VDUAL output is shut down. In the ISL6504A, the
5VDUAL output stays on during S4/S5 sleep states. This is
the only difference between the two parts; see Table 1.
An internal linear regulator supplies the 1.2V for the voltage
identification circuitry (VID) only during active states (S0 and
S1/S2), and uses the 3V3 pin as input source for its internal
pass element. Another internal regulator outputs a 1.5VSB
chip-set standby supply, which uses the 3V3DL pin as input
source for its internal pass element. The 3.3VDUAL/3.3VSB
and 1.5VSB outputs are active for as long as the ATX 5VSB
voltage is applied to the chip.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
PKG.
DWG. #
ISL6504CB
0 to 70 16 Ld Wide SOIC M16.3
ISL6504CR
0 to 70 20 Ld QFN
L20.6x6
ISL6504EVAL1 Evaluation Board
ISL6504ACB
0 to 70 16 Ld Wide SOIC M16.3
ISL6504ACR
0 to 70 20 Ld QFN
L20.6x6
ISL6504AEVAL1 Evaluation Board
Coming soon
0 to 70 16 Ld Narrow SOIC M16.15
Features
• Provides four ACPI-Controlled Voltages
- 5VDUAL USB/Keyboard/Mouse
- 3.3VDUAL/3.3VSB PCI/Auxiliary/LAN
- 1.2VVID Processor VID Circuitry
- 1.5VSB ICH4 Resume Well
• Excellent Output Voltage Regulation
- All Outputs: ±2.0% over temperature (as applicable)
• Small Size; Very Low External Component Count
• Undervoltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
• QFN Package:
- Near Chip Scale Package Footprint; Improved PCB
Efficiency; Thinner profile
Applications
• ACPI-Compliant Power Regulation for Motherboards
- ISL6504: 5VDUAL is shut down in S4/S5 sleep states
- ISL6504A: 5VDUAL stays on in S4/S5 sleep states
Pinouts
ISL6504/A (WIDE BODY SOIC)
TOP VIEW
1V5SB 1
3V3DLSB 2
3V3DL 3
1V2VID 4
3V3 5
S3 6
S5 7
GND 8
16 5VSB
15 VID_CT
14 VID_PG
13 SS
12 5VDL
11 5VDLSB
10 DLA
9 FAULT
NOTE: SOIC layout should accomodate both wide and narrow footprints.
ISL6504/A (6 X 6 QFN)
TOP VIEW
3V3DL 1
NC 2
1V2VID 3
3V3 4
S3 5
20 19 18 17 16
15 VID_PG
14 SS
13 NC
12 5VDL
11 5VDLSB
6 7 8 9 10
NOTE: The QFN bottom pad is electrically connected to the IC substrate, at
GND potential. It can be left unconnected, or connected to GND; do NOT
connect to another potential.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6504, ISL6504A
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3 (Continued)
PARAMETER
SYMBOL
3.3VDUAL/3.3VSB LINEAR REGULATOR (VOUT3)
Sleep State Regulation
TEST CONDITIONS
MIN TYP MAX UNITS
- - 2.0 %
3V3DL Nominal Voltage Level
3V3DL Undervoltage Rising Threshold
V3V3DL
- 3.3 -
- 2.75 -
V
V
3V3DL Undervoltage Hysteresis
- 150 -
mV
3V3DLSB Output Drive Current
5VDUAL SWITCH CONTROLLER (VOUT4)
5VDL Undervoltage Rising Threshold
I3V3DLSB V5VSB = 5V
58 -
- 4.10 -
mA
V
5VDL Undervoltage Hysteresis
- 200 -
mV
5VDLSB Output Drive Current
TIMING INTERVALS
I5VDLSB V5VDLSB = 4V, V5VSB = 5V
-20 - -40 mA
Active State Assessment Past Input UV
Thresholds (Note 3)
20 25 30
ms
Active-to-Sleep Control Input Delay
- 200 -
µs
VID_CT Charging Current
CONTROL I/O (S3, S5, FAULT)
IVID_CT VVID_CT = 0V
- 10 -
µA
High Level Input Threshold
- - 2.2 V
Low Level Input Threshold
0.8 -
-
V
S3, S5 Internal Pull-up Impedance to 5VSB
- 50 -
kΩ
FAULT Output Impedance
TEMPERATURE MONITOR
Fault-Level Threshold (Note 4)
Shutdown-Level Threshold (Note 4)
NOTES:
3. Guaranteed by Correlation.
4. Guaranteed by Design.
FAULT = high
- 100 -
125 -
- 155
-
-
Ω
oC
oC
5
5 Page 
ISL6504, ISL6504A
pins of the control IC, and connect them to ground through a
via placed close to the ground pad. Minimize any leakage
current paths from the SS node, as the internal current
source is only 10µA (typical).
+12VIN
+5VSB
C5VSB
CIN
CHF1
CSS
CBULK1
VOUT1
5VSB
SS 5VDLSB
5VDL
1V5SB
CBULK4
Q3
VOUT4
CHF4
Q1
CHF3
VOUT3
3V3DLSB
DLA
3V3DL
Q4
+5VIN
CBULK3
ISL6504/A
1V2VID
Q2 3V3 GND
CBULK2
VOUT2
CHF2
+3.3VIN
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT/POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 11. PRINTED CIRCUIT BOARD ISLANDS
A multi-layer printed circuit board is recommended.
Figure 11 shows the connections to most of the components
in the circuit. Note that the individual capacitors shown each
could represent numerous physical capacitors. Dedicate one
solid layer for a ground plane and make all critical
component ground connections through vias placed as close
to the component terminal as possible. Dedicate another
solid layer as a power plane and break this plane into
smaller islands of common voltage levels. Ideally, the power
plane should support both the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers to create power islands connecting the filtering
components (output capacitors) and the loads. Use the
remaining printed circuit layers for small signal wiring.
Component Selection Guidelines
Output Capacitors Selection
The output capacitors should be selected to allow the output
voltage to meet the dynamic regulation requirements of
active state operation (S0, S1). The load transient for the
various microprocessor system’s components may require
high quality capacitors to supply the high slew rate (di/dt)
current demands. Thus, it is recommended that the output
capacitors be selected for transient load regulation, paying
attention to their parasitic components (ESR, ESL).
Also, during the transition between active and sleep states
on the 3.3VDUAL/3.3VSB and 5VDUAL outputs, there is a
short interval of time during which none of the power pass
elements are conducting - during this time the output
capacitors have to supply all the output current. The output
voltage drop during this brief period of time can be easily
approximated with the following formula:
∆V O U T
=
IOUT
×
E
S
ROUT
+
C-----O--t--t-U----T-
, where
∆VOUT - output voltage drop
ESROUT - output capacitor bank ESR
IOUT - output current during transition
COUT - output capacitor bank capacitance
tt - active-to-sleep or sleep-to-active transition time (10µs typ.)
The output voltage drop is heavily dependent on the ESR
(equivalent series resistance) of the output capacitor bank,
the choice of capacitors should be such as to maintain the
output voltage above the lowest allowable regulation level.
Input Capacitors Selection
The input capacitors for an ISL6504/A application must have
a sufficiently low ESR so as not to allow the input voltage to
dip excessively when energy is transferred to the output
capacitors. If the ATX supply does not meet the
specifications, certain imbalances between the ATX’s
outputs and the ISL6504/A’s regulation levels could have as
a result a brisk transfer of energy from the input capacitors to
the supplied outputs. At the transition between active and
sleep states, such phenomena could be responsible for the
5VSB voltage drooping excessively and affecting the output
regulation. The solution to such a potential problem is using
larger input capacitors with a lower total combined ESR.
Transistor Selection/Considerations
The ISL6504/A usually requires one P-Channel (or bipolar
PNP), two N-Channel MOSFETs, and one bipolar NPN
transistors.
One important criteria for selection of transistors for all the
linear regulators/switching elements is package selection for
efficient removal of heat. The power dissipated in a linear
regulator or an ON/OFF switching element is
PLINEAR = IO × (VIN – VOUT)
Select a package and heatsink that maintains the junction
temperature below the rating with the maximum expected
ambient temperature.
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ISL6504.PDF ] | |
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