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PDF ISL6444 Data sheet ( Hoja de datos )
| Número de pieza | ISL6444 | |
| Descripción | Dual PWM Controller with DDR Memory Option for Gateway Applications | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
Data Sheet
May 2002
ISL6444
FN9069.1
Dual PWM Controller with DDR Memory
Option for Gateway Applications
The ISL6444 PWM controller provides high efficiency and
regulation for two output voltages adjustable in the range from
0.9V to 5.5V that are required to power I/O, chip-sets, and
memory banks in high-performance notebook computers,
PDAs, and Internet appliances.
Synchronous rectification and hysteretic operation at light
loads contribute to a high efficiency over a wide range of
loads. The hysteretic mode of operation can be disabled
separately on each PWM converter if continuous conduction
operation is desired for all load levels. Efficiency is even
further enhanced by using MOSFET’s RDS(ON) as a current
sense component.
Feed-forward ramp modulation, current mode control
scheme, and internal feed-back compensation provide fast
response to load transients. Out-of-phase operation with a
180o phase shift reduces the input current ripple.
The controller can be transformed in a complete DDR
memory power supply solution by activating a DDR pin. In
DDR mode of operation one of the channels tracks the
output voltage of another channel and provides output
current sink and source capability–features essential for
proper powering of DDR chips. The buffered reference
voltage required by this type of memory is also provided.
The ISL6444 monitors the output voltages. Each PWM
controller generates a PGOOD (power good) signal when
the soft-start is completed and the output is within ±10% of
the set point.
A built-in overvoltage protection prevents output voltage
from going above 115% of the set point. Normal operation
automatically restores when the overvoltage conditions go
away. Undervoltage protection latches the chip off when
either output drops below 75% of its set value after the soft-
start sequence for this output is completed. An adjustable
overcurrent function monitors the output current by sensing
the voltage drop across the lower MOSFET. If precision
current-sensing is required, an external current-sense
resistor may optionally be used.
The IC comes in a 28 lead SSOP package.
Ordering Information
PART NUMBER TEMP. (oC) PACKAGE
ISL6444CA
-10 to 85 28 Ld SSOP
ISL6444CA-T
-10 to 85
28 Ld SSOP
Taped and
Reeled
PKG. NO.
M28.15
M28.15
Features
• Provides regulated output voltage in the range 0.9V–5.5V
- High efficiency over wide load range
- Synchronous buck converter with hysteretic operation at
light load
• Complete DDR memory power solution
- VTT tracks VDDQ/2
- VDDQ/2 buffered reference output
• No current-sense resistor required
- Uses MOSFET’s RDS(ON)
- Optional current-sense resistor for precision overcurrent
• Undervoltage lock-out on VCC pin
• Dual mode operation
- Operates directly from battery 5.0-24V input
- Operates from 3.3V or 5V system rail
• Excellent dynamic response
- Combined voltage feed-forward and current mode
control
• Power-good signal for each channel
• 300kHz switching frequency
- Out-of-phase operation for reduced input ripple
- In-phase operation in DDR mode for reduced channel
interference
- Out-of-phase operation with 90o phase shift for two-
stage conversion in DDR mode
Applications
• Residential and Enterprise Gateways
• DSL Modems
• Routers and Switchers
Pinout
ISL6444 (SSOP-28)
GND
LGATE1
PGND1
PHASE1
UGATE1
BOOT1
ISEN1
EN1
1
2
3
4
5
6
7
8
VOUT1 9
VSEN1 10
OCSET1 11
SOFT1 12
DDR 13
VIN 14
28 VCC
27 LGATE2
26 PGND2
25 PHASE2
24 UGATE2
23 BOOT2
22 ISEN2
21 EN2
20 VOUT2
19 VSEN2
18 OCSET2
17 SOFT2
16 PG2/REF
15 PG1
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1 page  
Block Diagram
BOOT1
UGATE1
PHASE1
UG1
OVP1
HI
LGATE1
PGND1
GATE
CONTROL
VCC
LG1
OVP1
GATE LOGIC
LO
MODE CHANGE COMP 1
-
HYST COMP 1
-
SOFT1 EN1 EN2 SOFT2
REFERENCE
AND
SOFT START
SDWN1
SDWN2
REF=0.9V
UG2
HI
OVP2
GATE LOGIC
LO
GATE
CONTROL
VCC
LG2
OVP2
MODE CHANGE COMP 2
-
HYST COMP 2
-
BOOT2
UGATE2
PHASE2
LGATE2
PGND2
VSEN1
VREF
ISEN1
EA1
--
Σ-
LGATE1
LGATE1
- CSA1
OC COMP1
- OC LOGIC1
-Σ
EA2
--
OC COMP2
OC LOGIC2
-
LGATE2
CSA2
-
S2e
LGATE2
VCC
GND
VSEN1 OVP1
OUTPUT
VOLTAGE
MONITOR
PG1
OCSET1
1.24V
RAMP 1
ϕ=90o
S1
S2a
ϕ=0o CLK ϕ=180o RAMP 2
S2b VCC
VIN
1.24V
S2c
OVP2 VSEN2
OUTPUT
VOLTAGE
MONITOR
-
S2d
OCSET2
PG2/REF
VSEN2
ISEN2
DDR
5 Page 
ISL6444
Overtemperature Protection
The chip incorporates an over temperature protection circuit
that shuts the chip down when the die temperature of 150oC
is reached. Normal operation restores at die temperatures
below 125oC through the full soft-start cycle.
DDR Application
Double Data Rate (DDR) memory chips are expected to take
a place of memory of choice in many newly designed
computers including high-end notebooks due to increased
throughput. A novelty feature associated with this type of
memory is new referencing and data bus termination
techniques. These techniques employ a reference voltage,
VREF, that tracks the center point of VDDQ and VSS
voltages and an additional VTT power source to which all
terminating resistors are connected. Despite the additional
power source, the overall memory power consumption is
reduced compared to traditional termination.
The added power source has a cluster of requirements that
should be observed and considered. Due to reduced
differential thresholds of DDR memory, the termination
power supply voltage, VTT, shall closely track VDDQ/2
voltage. Another very important feature for the termination
power supply is a capability to equally operate in sourcing
and sinking modes. The VTT supply shall regulate the output
voltage with the same degree of precision when current is
floating from the supply to the load and when the current is
diverted back from the load into the power supply. The last
mode of operation usually conflicts with the way most PWM
controllers operate.
The ISL6444 dual channel PWM controller possesses
several important means that allow re configuration for this
particular application and provide all three voltages required
in DDR memory compliant computer.
To reconfigure the ISL6444 for a complete DDR solution, the
DDR pin shall be permanently set high. The simplest way to
do that is to connect it to the VCC rail. This activates some
functions inside the chip that are specific to the DDR
memory power needs.
In DDR application presented in Figure 12, the first controller
regulates VDDQ rail to 2.5V. The output voltage is set by an
external divider R3 and R4. The second controller regulates
the VTT rail to VDDQ/2. The OCSET2 pin function is now
different. The pin serves now as an input that brings VDDQ/2
voltage created by R5 and R6 divider inside the chip. That
effectively provides a tracking function for the VTT voltage.
The PG2 pin function is also different in DDR mode. This pin
becomes the output of the buffer, which input is connected
via the OCSET2 pin to the center point of the R/R divider
from the VDDQ output. The buffer output voltage serves as
1.25V reference for the DDR memory chips. Current
capability of this pin is about 10mA.
For the VTT channel some control and protective functions
can be significantly simplified as this output is derived from
the VDDQ output. For example, the overcurrent and
overvoltage protections for the second controller are
disabled when the DDR pin is set high. The hysteretic mode
of operation is also disabled on the VTT channel to allow
sinking capability to be independent from the load level. As
the VTT channel tracks the VDDQ/2 voltage, the soft-start
function is not required and the SOFT2 pin may be left open
or may be connected to VCC.
Channel Synchronization in DDR
Applications
Presence of two PWM controllers on the same die require
channel synchronization to reduce inter channel interference
that may cause the duty factor jitter and increased output
ripple. The PWM controller is mostly susceptible to noise
when an error signal on the input of the PWM comparator
approaches the decision making point. False triggering can
occur causing jitter and affecting the output regulation.
Out-of-phase operation is a common approach to
synchronize dual channel converters as it reduces an input
current ripple and provides a minimum interference for
channels that control different voltage levels. When used in
DDR application with cascaded converters (VTT generated
from VDDQ), the turn-on of the upper MOSFET in the VDDQ
channel happens to be just before the decision making point
in the VTT channel that is running with a duty-factor close to
50%, Figure 7 and Figure 8. This makes out-of-phase
channel synchronization undesirable when one of the
channels is running on a duty-factor of 50%. Inversely, the
in-phase channel arrangement does not have this drawback.
Points of decision are far from noisy moments of time in both
sourcing and sinking modes of operation for Vin=7.5V to 24V
as it is shown in Figure 7.
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ISL6444.PDF ] | |
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