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ISL6431ACB の電気的特性と機能

ISL6431ACBのメーカーはIntersil Corporationです、この部品の機能は「Advanced Pulse Width Modulation (PWM) Controller for Broadband Applications」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL6431ACB
部品説明 Advanced Pulse Width Modulation (PWM) Controller for Broadband Applications
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ISL6431ACB Datasheet, ISL6431ACB PDF,ピン配置, 機能
®
Data Sheet
October 2002
ISL6431A
FN9088
Advanced Pulse Width Modulation (PWM)
Controller for Broadband Applications
The ISL6431A is a high efficiency, fixed frequency,
synchronous buck PWM controller. It is designed for use in
applications that convert 5V to lower distributed voltages
required for DSL modems, cable and DSL routers and
broadband gateway core processor, memory and peripheral
power supplies.
The ISL6431A makes simple work out of implementing a
complete control and protection scheme for a DC-DC
stepdown converter. Designed to drive N-channel MOSFETs
in a synchronous buck topology, the ISL6431A integrates
the control, output adjustment, monitoring and protection
functions into a single 8-Lead package.
The ISL6431A provides simple, single feedback loop,
voltage-mode control with fast transient response. The
output voltage can be precisely regulated to as low as 0.8V,
with a maximum tolerance of ±1.5% over temperature and
line voltage variations. The device is capable of sinking, as
well as sourcing current. A fixed frequency oscillator reduces
design complexity, while balancing typical application cost
and efficiency.
The error amplifier features a 15MHz gain-bandwidth
product and 8V/µs slew rate which enables high converter
bandwidth for fast transient performance. The resulting
PWM duty cycles range from 0% to 100%.
Protection from overcurrent conditions is provided by
monitoring the rDS(ON) of the upper MOSFET to inhibit PWM
operation appropriately. This approach simplifies the
implementation and improves efficiency by eliminating the
need for a current sense resistor.
Ordering Information
TEMP. RANGE
PART NUMBER
(oC)
PACKAGE
ISL6431ACB
ISL6431EVAL1
0 to 70 8 Ld SOIC
Evaluation Board
PKG.
NO.
M8.15
Features
• Operates from +5V Input
• 0.8V to VIN Output Range
- 0.8V Internal Reference
- ±1.5% Over Line Voltage and Temperature
• Drives N-Channel MOSFETs
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Cycle
• Lossless, Programmable Overcurrent Protection
- Uses Upper MOSFET’s rDS(on)
• Converter Can Source and Sink Current
• Small Converter Size
- 300kHz Fixed Frequency Oscillator
- Internal Soft Start
- 8-Lead SOIC Package
Applications
• Cable/DSL Routers and DSL Modems
• DSP and Core Communications Processor Supplies
• Broadband Gateways
• Memory Supplies
• Industrial Power Supplies
• 5V-Input DC-DC Regulators
• Low-Voltage Distributed Power Supplies
Pinout
BOOT 1
UGATE 2
GND 3
LGATE 4
8 PHASE
7 COMP/OCSET
6 FB
5 VCC
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL6431ACB pdf, ピン配列
ISL6431A
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
Absolute Boot Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . +15.0V
Upper Driver Supply Voltage, VBOOT - VPHASE . . . . . . . . . . . +6.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . -40oC to 85oC
Junction Temperature Range . . . . . . . . . . . . . . . . . -40oC to 125oC
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER
Recommended Operating Conditions, Unless Otherwise Noted. VCC = 5.0V ±5% and TA = 25oC
SYMBOL
TEST CONDITIONS
MIN TYP MAX
VCC SUPPLY CURRENT
Nominal Supply
POWER-ON RESET
IVCC
2.6 3.2 3.8
Rising VCC POR Threshold
POR
4.19 4.30 4.50
VCC POR Threshold Hysteresis
0.01 0.20 0.85
OSCILLATOR
Frequency
Ramp Amplitude
REFERENCE
fOSC
VOSC
VCC = 5V
250 300 340
- 1.5 -
Reference Voltage Tolerance
Nominal Reference Voltage
VREF
- - 1.5
- 0.800 -
ERROR AMPLIFIER
DC Gain
- 82 -
Gain-Bandwidth Product
GBWP
14 -
-
Slew Rate
SR COMP = 10pF
4.65 8.0
9.2
GATE DRIVERS
Upper Gate Source Current
Upper Gate Sink Current
Lower Gate Source Current
Lower Gate Sink Current
PROTECTION / DISABLE
IUGATE-
SRC
VBOOT - VPHASE = 5V, VUGATE = 4V
IUGATE-SNK
ILGATE-SRC VVCC = 5V, VLGATE = 4V
ILGATE-SNK
- -1 -
-1-
- -1 -
-2-
OCSET Current Source
Disable Threshold
IOCSET
VDISABLE
17 20 22
- - 0.8
UNITS
mA
V
V
kHz
VP-P
%
V
dB
MHz
V/µs
A
A
A
A
µA
V
3


3Pages


ISL6431ACB 電子部品, 半導体
ISL6431A
ISL6431A
VIN
UGATE
PHASE
LGATE
Q1
Q2
LO VOUT
CIN
CO
RETURN
FIGURE 3. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
Figure 3 shows the critical power components of the converter.
To minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of a ground or power
plane in a printed circuit board. The components shown in
Figure 3 should be located as close together as possible.
Please note that the capacitors CIN and CO may each
represent numerous physical capacitors. Locate the ISL6431A
within 3 inches of the MOSFETs, Q1 and Q2. The circuit traces
for the MOSFETs’ gate and source connections from the
ISL6431A must be sized to handle up to 1A peak current.
Figure 4 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the COMP/OCSET pin and locate the
resistor, ROSCET close to the COMP/OCSET pin because
the internal current source is only 20µA. Provide local VCC
decoupling between VCC and GND pins. Locate the
capacitor, CBOOT as close as practical to the BOOT and
PHASE pins. All components used for feedback
compensation should be located as close to the IC a
practical.
BOOT
D1
+5V CBOOT
ISL6431A
PHASE
VCC
+5V
COMP/OCSET
CVCC
GND
+VIN
Q1 LO
Q2 CO
VOUT
FIGURE 4. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Feedback Compensation
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level. The
error amplifier (Error Amp) output (VE/A) is compared with
the oscillator (OSC) triangular wave to provide a
pulse-width modulated (PWM) wave with an amplitude of
VIN at the PHASE node. The PWM wave is smoothed by the
output filter (LO and CO).
OSC
PWM
COMPARATOR
VOSC
-
+
DRIVER
DRIVER
VIN
LO
PHASE CO
VOUT
ZFB
VE/A
-
+
ZIN
ERROR REFERENCE
AMP
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C2
C1 R2
ZFB
VOUT
ZIN
C3 R3
COMP
FB
-
+
ISL6431A
REFERENCE
R1
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A. This function is dominated by a DC
Gain and the output filter (LO and CO), with a double pole
break frequency at FLC and a zero at FESR. The DC Gain of
the modulator is simply the input voltage (VIN) divided by the
peak-to-peak oscillator voltage VOSC.
Modulator Break Frequency Equations
FLC=
--------------------1----------------------
2π x LO x CO
FESR= 2----π------x-----E----S--1---R------x-----C-----O---
The compensation network consists of the error amplifier
(internal to the ISL6431A) and the impedance networks ZIN
and ZFB. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f0dB and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 7. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth.
2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC).
3. Place 2ND Zero at Filter’s Double Pole.
4. Place 1ST Pole at the ESR Zero.
6

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部品番号部品説明メーカ
ISL6431ACB

Advanced Pulse Width Modulation (PWM) Controller for Broadband Applications

Intersil Corporation
Intersil Corporation


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