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ISL6405EEB の電気的特性と機能

ISL6405EEBのメーカーはIntersil Corporationです、この部品の機能は「Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-top Box Designs」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL6405EEB
部品説明 Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-top Box Designs
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ISL6405EEB Datasheet, ISL6405EEB PDF,ピン配置, 機能
®
Data Sheet
February 2003
ISL6405
FN9026
Dual Output LNB Supply and Control
Voltage Regulator with I2C Interface for
Advanced Satellite Set-top Box Designs
The ISL6405 is a highly integrated voltage regulator and
interface IC, specifically designed for supplying power and
control signals from advanced satellite set-top box (STB)
modules to the low noise blocks (LNBs) of two antenna
ports. The device is comprised of two independent current-
mode boost PWMs and two low-noise linear regulators along
with the circuitry required for 22Khz tone generation,
modulation and I2C device interface. The device makes the
total LNB supply design simple, efficient and compact with
low external component count.
Two independent current-mode boost converters provide the
linear regulators with input voltages that are set to the final
output voltages, plus typically 1.2V to insure minimum power
dissipation across each linear regulator. This maintains
constant voltage drops across each linear pass element
while permitting adequate voltage range for tone injection.
The final regulated output voltages are available at two
output terminals to support simultaneous operation of two
antenna ports for dual tuners. The outputs for each PWM are
set to 13V or 18V by independent voltage select commands
(VSEL1, VSEL2) through the I2C bus. Additionally, to
compensate for the voltage drop in the coaxial cable, the
selected voltage may be increased by 1V with the line length
compensation (LLC) feature. All the functions on this IC are
controlled via the I2C bus by writing 8 bits on System
Register (SR, 8 bits). The same register can be read back,
and two bits will report the diagnostic status. Separate enable
commands sent on the I2C bus provide independent standby
mode control for each PWM and linear combination, disabling
the output into shutdown mode.
Each output channel is capable of providing 750mA of
continuous current. The overcurrent limit can be digitally
programmed The SEL18V pin with QFN package allows the
13V to 18V transition with an external pin, over-riding the I2C
input.
Ordering Information
TEMP. RANGE
PART NUMBER
(oC)
PACKAGE
ISL6405EEB
ISL6405ER
-20 to 85
-20 to 85
28 LD EPSOIC
32 QFN
PKG. NO.
M28.3B
L32.5x5
Features
• Single Chip Power solution
- True Dual Operation for 2-Tuner / 2-Dish Applications
- Both Outputs May be Enabled Simultaneously at
Maximum Power
- Integrated DC-DC Converter and I2C Interface
• Switch-Mode Power Converter for Lowest Dissipation
- Boost PWMs with > 92% Efficiency
- Selectable 13V or 18V Outputs
- Digital Cable Length Compensation (1V)
• I2C Compatible Interface for Remote Device Control
- Registered Slave Address 0001 00XX
- Full 3.3V / 5V Operation up to 400kHz
• Built-In Tone Oscillator Factory Trimmed to 22kHz
- Facilitates DiSEqCTM (EUTELSAT) Encoding
• Internal Over-Temperature Protection and Diagnostics
• Internal Overload and Overtemp Flags (Visible on I2C)
• LNB Short-Circuit Protection and Diagnostics
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Product Outline
- Near Chip-Scale Package Footprint
• External Pins to Select 13V / 18V Options
- Available with QFN Package Only
Applications
• LNB Power Supply and Control for Satellite Set-Top Box
References
Tech Brief 389 (TB389) - “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”; Available on
the Intersil website, www.intersil.com
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved

1 Page





ISL6405EEB pdf, ピン配列
Block Diagram
COUNTER
10 GATE1
OVERCURRENT
PROTECTION
LOGIC SCHEME 1
OLF1
DCL
PWM
LOGIC
Q
S
CLK1
OC1
PGND1
9
CS1
11
CS ILIM1
AMP
SLOPE
COMPENSATION
13 COMP1
FB1
12
VREF1
14 VSW1
20 VO1
15 16 17
OLF2
DCL
OVERCURRENT
PROTECTION
LOGIC SCHEME 2
COUNTER
OC2
SDA
ADDR SCL
ISEL1
EN1
ENT1
OTF
LLC1
OLF
I2C
INTERFACE
VSEL1
VSEL2
ISEL2
EN2
ENT2
DCL
LLC2
CLK2
PWM
LOGIC
Q
S
ILIM2 CS
AMP
SLOPE
COMPENSATION
GATE2
PGND2
CS2
BAND GAP
REF VOLTAGE
REF
VOLTAGE
ADJ1
BGV
CLK1
OSC. CLK2
220kHZ
÷ 10 &
WAVE SHAPING
TONE
INJ
CKT 1
22kHZ
TONE
TONE
INJ
CKT 2
BGV
REF
VOLTAGE
ADJ2
VREF2
COMP2
FB2
VSW2
4
5
6
2
3
1
+
VO2
22
+-
- ENT2
28 VCC
ON CHIP
LINEAR
UVLO
SGND
POR
7 SOFT-START
INT 5V
SOFT-START
EN1/EN2
8
ENT1
CPVOUT
27
OTF
THERMAL
SHUTDOWN
CPSWIN
CHARGE PUMP
CPSWOUT
26
21 18 19 23 24
25


3Pages


ISL6405EEB 電子部品, 半導体
ISL6405
Electrical Specifications
Vcc = 12V, TA = -20oC to +85oC, unless otherwise noted.Typical values are at TA = 25oC.EN1=EN2=H,
LLC1=LLC2=L, ENT1=ENT2=L, DCL=L, DSQIN1=DSQIN2=L, Iout = 12mA, unless otherwise noted. See
software description section for I2C access to the system. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
DSQIN PIN
DSQIN pin logic Low
1.5V
V
DSQIN pin Logic HIGH
DSQIN pin Input Current
3.5
1
V
µA
CURRENT SENSE
Current Limiting Threshold (max. input)
(Note 5)
150 200 250
mV
Input Bias Current
Over Current Threshold
IBIAS
Static current mode, DCL = H
- 700 -
325 400 500
nA
mV
ERROR AMPLIFIER
Open Loop Voltage Gain
Gain Bandwidth Product
PWM
AOL (Note 5)
GBP (Note 5)
70 88
-
dB
10 -
- MHz
Maximum Duty Cycle
90 93
-
%
Minimum Pulse Width
(Note 5)
- 20 -
nS
OSCILLATOR
Oscillator Frequency
Thermal Shutdown
fo Fixed at (10)(ftone)
200 220 240
kHz
Temperature Shutdown Threshold
(Note 5)
150
Temperature Shutdown Hysteresis
(Note 5)
20
NOTES:
3. Internal Digital Soft-start
4. VO1 for LNB1, VO2 for LNB2. Voltage programming signals VSEL1, VSEL2, LLC1, and LLC2 are implemented via the I2C bus.
IO1 = IO2 = 350mA / 750mA.
5. Guaranteed by Design
Functional Pin Description
SYMBOL
SDA
SCL
FUNCTION
Bi-directional data from/to I2C bus.
Clock from I2C bus.
VSW1, 2 Input of the linear post-regulator.
PGND1, 2 Dedicated ground for the output gate driver of
respective PWM.
CS1, 2
Current sense input; connect Rsc at this pin for
desired over current value for respective PWM.
SGND
Small signal ground for the IC.
AGND
Analog ground for the IC.
TCAP1, 2
Capacitor for setting rise and fall time of the output
of LNB A and LNB B respectively.
BYPASS Bypass capacitor for internal 5V.
DSQIN1, 2
When HIGH enables internal 22kHz modulation for
LNB A and LNA B respectively, Use this pin for tone
enable function for LNB A and LNB B.
VCC
Main power supply to the chip.
GATE1, 2
These are the device outputs of PWM A and PWM B
respectively. These high current driver outputs are
capable of driving the gate of a power FET. These
outputs are actively held low when Vcc is below the
UVLO threshold.
VO1, 2
Output voltage of LNB A and LNB B respectively.
Functional Pin Description (Continued)
SYMBOL
FUNCTION
ADDRESS Address pin to select two different addresses per
voltage level at this pin.
COMP1, 2 Error amp outputs used for compensation.
FB1, 2
Feedback pins for respective PWMs
CPVOUT, Charge pump connections.
CPSWIN,
CPSWOUT
SEL18V1, 2 When connected HIGH, this pin will change the
output of the respective PWM to 18V. Only available
on the QFN package option.
6

6 Page



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部品番号部品説明メーカ
ISL6405EEB

Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-top Box Designs

Intersil Corporation
Intersil Corporation


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