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PDF ISL6244HRZ Data sheet ( Hoja de datos )
| Número de pieza | ISL6244HRZ | |
| Descripción | Multi-Phase PWM Controller | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
November 2003
ISL6244
FN9106.1
Multi-Phase PWM Controller
The ISL6244 provides core-voltage regulation by driving 2 to
4 interleaved synchronous-rectified buck-converter channels
in parallel. Interleaving the channel timing results in
increased ripple frequency which reduces input and output
ripple currents. The reduction in ripple results in lower
component cost, reduced dissipation, and a smaller
implementation area.
The ISL6244 uses cost and space-saving rDS(ON) sensing
for channel current balance, active voltage positioning, and
over-current protection. Output voltage is monitored by an
internal differential remote sense amplifier. A high-bandwidth
error amplifier drives the output voltage to match the
programmed 5-bit DAC reference voltage. The resulting
compensation signal guides the creation of pulse width
modulated (PWM) signals to control companion Intersil
MOSFET drivers. The OFS pin allows direct offset of the
DAC voltage from 0V to 100mV using a single external
resistor. The entire system is trimmed to ensure a system
accuracy of ± 1%.
Outstanding features of this controller IC include
Dynamic VIDTM technology allowing seamless on-the-fly VID
changing without the need of any external components.
Battery “feed-forward” is provided to allow for traditional
control schemes over total input voltage variation. Output
voltage “droop” or active voltage positioning is optional.
When employed, it allows the reduction in size and cost of
the output capacitors required to support load transients. A
threshold-sensitive enable input allows the use of an
external resistor divider for start-up coordination with Intersil
MOSFET drivers or any other devices powered from a
separate supply.
Superior over-voltage protection is achieved by gating on the
lower MOSFET of all phases to reduce the output voltage.
Under-voltage conditions are detected, but PWM operation
is not disrupted. Over-current conditions cause a hiccup-
mode response as the controller repeatedly tries to restart.
After a set number of failed startup attempts, the controller
latches off. A power good logic signal indicates when the
converter output is between the UV and OV thresholds.
Features
• Multi-Phase Power Conversion
- 2, 3 or 4 Phase Operation
• Active Channel Current Balancing
• Precision rDS(ON) Current Sharing
- Lossless
- Low Cost
• Precision CORE Voltage Regulation
- Differential Remote Output Voltage Sensing
- Programmable Reference Offset
- ± 1% System Accuracy
• Microprocessor Voltage Identification Input
- 5-Bit VID Input
- 0.800V to 1.550V in 25mV Steps
- Dynamic VID Technology
• Programmable Droop Voltage
• Excellent Dynamic Response
- Combined Input Voltage Feed-Forward and Pulse-by-
Pulse Average Current Mode
• Over Current Protection
• Digital Soft Start
• Threshold Sensitive Enable Input
• High Ripple Frequency (160kHz to 4MHz)
• Lead-free product now available suffix (Z)
• QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package footprint, which improves PCB
efficiency and has a thinner profile
Applications
• AMD Hammer Family Processor Voltage Regulator
• Low Output Voltage, High Current DC-DC Converters
• Voltage Regulator Modules
Ordering Information
PART NUMBER TEMP. (oC) PACKAGE
PKG. DWG. #
ISL6244CR
0 to 70 32 Ld 5x5 QFN L32.5x5
ISL6244CRZ
0 to 70 32 Ld 5x5 QFN L32.5x5
ISL6244HR
-10 to 100 32 Ld 5x5 QFN L32.5x5
ISL6244HRZ
-10 to 100 32 Ld 5x5 QFN L32.5x5
NOTE: Add “-T” suffix for 32 QFN 5x5 Tape and Reel packages.
Intersil Lead Free products employ special lead free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which is compatible with both SnPb and lead free
soldering operations. Intersil Lead Free products are MSL classified
at lead free peak reflow temperatures that meet or exceed the lead
free requirements of IPC/JEDEC J Std-020B.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Dynamic VID™ is a trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6244
Typical Operating Performance (Continued)
FIGURE 3. INRUSH CURRENT AT VIN 10.8V @ 52A
FIGURE 4. TRANSIENT WAVEFORM FROM 0A TO 52A
FIGURE 5. INDUCTOR CURRENT TRANSIENT
1.650
Vo+ (AMD SPEC)
1.600
1.550
1.500
Vo- (AMD SPEC)
1.450
TARGET
VBAT 8.4V
1.400
0 20 40
OUTPUT CURRENT (A)
FIGURE 7. ISL6244 DROOP: VBAT = 8.4V
60
5
FIGURE 6. VID CHANGES FROM 1.60V TO 1.20V
FIGURE 8. FOUR PHASE CURRENT BALANCE @ 52A
5 Page 
ISL6244
PWM Operation
The timing of each converter leg is set by the number of
active channels. The default channel setting for the ISL6244
is four. One switching cycle is defined as the time between
PWM1 pulse termination signals. The pulse termination
signal is an internally generated clock signal which triggers
the falling edge of PWM1. The cycle time of the pulse
termination signal is the inverse of the switching frequency
set by the resistor between the FS pin and ground. Each
cycle begins when the clock signal commands the channel-1
PWM output to go low. The PWM1 transition signals the
channel-1 MOSFET driver to turn off the channel-1 upper
MOSFET and turn on the channel-1 synchronous MOSFET.
In the default channel configuration, the PWM2 pulse
terminates 1/4 of a cycle after PWM1. The PWM 3 output
follows another 1/4 of a cycle after PWM2. PWM4 terminates
another 1/4 of a cycle after PWM3.
If PWM3 is connected to VCC, then two channel operation is
selected and the PWM2 pulse terminates 1/2 of a cycle later.
Connecting PWM4 to VCC selects three channel operation and
the pulse-termination times are spaced in 1/3 cycle increments.
Once a PWM signal transitions low, it is held low for a
minimum of 1/4 cycle. This forced off time is required to
ensure an accurate current sample. Current sensing is
described in the next section. After the forced off time
expires, the PWM output is enabled. The PWM output state
is driven by the position of the error amplifier output signal,
VCOMP, minus the current correction signal relative to the
sawtooth ramp as illustrated in Figure 1. When the modified
VCOMP voltage crosses the sawtooth ramp, the PWM output
transitions high. The MOSFET driver detects the change in
state of the PWM signal and turns off the synchronous
MOSFET and turns on the upper MOSFET. The PWM signal
will remain high until the pulse termination signal marks the
beginning of the next cycle by triggering the PWM signal low.
Current Sensing
During the forced off time following a PWM transition low,
the controller senses channel load current by sampling the
voltage across the lower MOSFET rDS(ON), see Figure 15. A
ground-referenced amplifier, internal to the ISL6244,
connects to the PHASE node through a resistor, RISEN. The
voltage across RISEN is equivalent to the voltage drop
across the rDS(ON) of the lower MOSFET while it is
conducting. The resulting current into the ISEN pin is
proportional to the channel current, IL. The ISEN current is
then sampled and held after sufficient settling time every
switching cycle. The sampled current, In, is used for
channel-current balance, load-line regulation and
overcurrent protection. From Figure 15, the following
equation for In is derived
In
=
IL
r---D----S----(--O----N-----)
RISEN
(EQ. 3)
where IL is the channel current.
If rDS(ON) sensing is not desired, an independent current-
sense resistor in series with the lower MOSFET source can
serve as a sense element. The circuitry shown in Figure 15
represents channel n of an N-channel converter. This
circuitry is repeated for each channel in the converter, but
may not be active depending upon the status of the PWM3
and PWM4 pins as described in the previous section.
In
ISEN
=
IL
-r--D-----S----(---O-----N-----)
RISEN
VIN
CHANNEL N
UPPER MOSFET
SAMPLE
&
HOLD
-
+
IL
ISEN(n)
RISEN
-
IL rDS(ON)
+
CHANNEL N
LOWER MOSFET
ISL6244 INTERNAL CIRCUIT EXTERNAL CIRCUIT
FIGURE 15. INTERNAL AND EXTERNAL CURRENT-SENSING
CIRCUITRY
Channel-Current Balance
The sampled current, In, from each active channel is used to
gauge both overall load current and the relative channel
current carried in each leg of the converter. The individual
sample currents are summed and divided by the number of
active channels. The resulting average current, IAVG,
provides a measure of the total load current demand on the
converter and the appropriate level of channel current. Using
Figures 15 and 16, the average current is defined as:
IAVG
=
-I-1-----+-----I--2----+-----…-------I--N--
N
IAVG
=
-I-O-----U----T--
N
r---D----S----(--O----N-----)
RISEN
(EQ. 4)
where N is the number of active channels and IOUT is the
total load current.
The average current is then subtracted from the individual
channel sample currents. The resulting error current, IER, is
then filtered before it adjusts VCOMP. The modified VCOMP
signal is compared to a sawtooth ramp signal and produces
a pulse width which corrects for any imbalance and drives
the error current toward zero. Figure 16 illustrates Intersil’s
patented current-balance method as implemented on
channel-1 of a multi-phase converter.
11
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| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet ISL6244HRZ.PDF ] | |
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