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ISL6225 の電気的特性と機能

ISL6225のメーカーはIntersil Corporationです、この部品の機能は「Dual Mobile-Friendly PWM Controller with DDR Memory Option」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL6225
部品説明 Dual Mobile-Friendly PWM Controller with DDR Memory Option
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ISL6225 Datasheet, ISL6225 PDF,ピン配置, 機能
®
Data Sheet
September 2003
ISL6225
FN9049.4
Dual Mobile-Friendly PWM Controller with
DDR Memory Option
The ISL6225 dual PWM controller delivers high efficiency and
tight regulation from two voltage regulating synchronous buck
DC/DC converters. The ISL6225 PWM power supply controller
was designed especially for DDR DRAM, SDRAM, and graphic
chipset applications in high performance desknote PCs,
notebook PCs, sub-notebook PCs, and PDAs.
Automatic mode selection of constant-frequency synchronous
rectification at heavy load, and hysteretic diode-emulation at
light load, assure high efficiency over a wide range of
conditions. The hysteretic mode of operation can be disabled
separately on each PWM converter if constant-frequency
continuous-conduction operation is desired for all load levels.
Efficiency is further enhanced by using the lower MOSFET
RDS(ON) as the current sense element.
Voltage-feed-forward ramp modulation, average current mode
control, and internal feedback compensation provide fast
response to input voltage and output load transients. Input
current ripple is minimized by channel to channel PWM
phase shift of 0°, 90°, or 180° determined by input voltage
and status of the DDR pin.
The ISL6225 can control two independent output voltages
adjustable from 0.9V to 5.5V or, by activating the DDR pin,
transform into a complete DDR memory power supply
solution. In DDR mode, CH2 output voltage VTT tracks CH1
output voltage VDDQ. CH2 output can both source and sink
current, an essential power supply feature for DDR memory
systems. The reference voltage VREF required by DDR
memory is generated as well.
In dual power supply applications the ISL6225 monitors the
output voltage of both CH1 and CH2. An independent
PGOOD (power good) signal is asserted for each channel
after the soft-start sequence has completed, and the output
voltage is within ±10% of the set point. In DDR mode CH1
generates the only PGOOD signal.
Built-in over-voltage protection prevents the output from
going above 115% of the set point by holding the lower
MOSFET on and the upper MOSFET off. When the output
voltage decays below the over-voltage threshold, normal
operation automatically resumes. Once the soft-start
sequence has completed, under-voltage protection may
latch the ISL6225 off if either output drops below 75% of its
set point value.
Adjustable over-current protection (OCP) monitors the
voltage drop across the RDS(ON) of the lower MOSFET. If
more precise current-sensing is required, an external current
sense resistor may be used.
Ordering Information
PART NUMBER TEMP. (oC) PACKAGE
PKG. NO.
ISL6225CA
-10 to 85
28 Ld SSOP
M28.15
ISL6225CA-T
-10 to 85 28 Ld SSOP Tape
and Reel
M28.15
Features
• Provides regulated output voltage in the range of 0.9V-5.5V
- High efficiency over wide load range
- Synchronous buck converter with hysteretic operation at
light load
- Inhibit Hysteretic mode on one, or both channels
• Complete DDR memory power solution
- VTT tracks VDDQ/2
- VDDQ/2 buffered reference output
• No current-sense resistor required
- Uses MOSFET RDS(ON)
- Optional current-sense resistor for precision Over-Current
• Under-voltage lock-out on VCC pin
• Dual input voltage mode operation
- Operates directly from battery 5V to 24V input
- Operates from 3.3V or 5V system rail
- VCC from 5V only
• Excellent dynamic response
- Combined voltage feed-forward and average current
mode control
• Power-good signal for each channel
• 300kHz switching frequency
- 180° channel to channel phase operation for reduced input
ripple when not in DDR mode
- 0° channel to channel phase operation in DDR mode for
reduced channel interference
- 90° channel to channel phase operation for reduced input
ripple in DDR mode when VIN is at GND.
Applications
Mobile PCs
• PDAs
• Hand-held portable instruments
Pinout
ISL6225
SSOP-28
TOP VIEW
GND 1
28 VCC
LGATE1 2
27 LGATE2
PGND1 3
26 PGND2
PHASE1 4
25 PHASE2
UGATE1 5
24 UGATE2
BOOT1 6
23 BOOT2
ISEN1 7
22 ISEN2
EN1 8
21 EN2
VOUT1 9
20 VOUT2
VSEN1 10
19 VSEN2
OCSET1 11
18 OCSET2
SOFT1 12
17 SOFT2
DDR 13
16 PG2/REF
VIN 14
15 PG1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL6225 pdf, ピン配列
ISL6225
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
Under-Voltage Shut-Down Level
Over-Voltage Shut-Down
GATE DRIVERS
VUVL
VOVP1
Fraction of the set point; ~2µs noise filter
Fraction of the set point; ~2µs noise filter
70
110
Upper Drive Pull-Up Resistance
R2UGPUP
Upper Drive Pull-Down Resistance
R2UGPDN
Lower Drive Pull-Up Resistance
R2LGPUP
Lower Drive Pull-Down Resistance
R2LGPDN
POWER GOOD AND CONTROL FUNCTIONS
VCC=4.5V
VCC=4.5V
VCC=4.5V
VCC=4.5V
-
-
-
-
Power Good Lower Threshold
Power Good Higher Threshold
VPG-
VPG+
Fraction of the set point; ~3µs noise filter
Fraction of the set point; ~3µs noise filter.
Guaranteed by design.
-13
12
PGOODx Leakage Current
PGOODx Voltage Low
EN - Low (Off)
IPGLKG
VPGOOD
VPULLUP = 5.5V
IPGOOD = -4mA
-
-
-
EN - High (On)
2.5
CCM Enforced (Hysteretic Operation
Inhibited)
VOUTX pulled low
-
Automatic CCM/Hysteretic Operation Enabled
VOUTX connected to the output
0.9
DDR - Low (Off)
-
DDR - High (On)
2.5
DDR REF Output Voltage
DDR REF Output Current
VDDREF DDR=1, IREF=0...10mA
IDDREF DDR=1. Guaranteed by design.
0.99*
VOC2
-
TYP
-
8
3.2
8
1.8
-
-
-
0.5
-
-
-
-
-
-
VOC2
10
MAX
85
130
15
5
15
3
-7
16
1
0.85
0.8
-
0.1
-
0.8
-
1.01*
VOC2
16
UNITS
%
%
%
%
µA
V
V
V
V
V
V
V
V
mA
3


3Pages


ISL6225 電子部品, 半導体
Block Diagram
BOOT1
UGATE1
SOFT1
PG1 EN1 VOUT1
VCC GND
VOUT2 EN2 REF/PG2 SOFT2
BOOT2
UGATE2
PHASE1
PGND1
LGATE1
ADAPTIVE DEAD-TIME
DIODE EMULATION
V/I SAMPLE TIMING
PWM/HYS TRANSITION
DDR=1
DDR=0
ADAPTIVE DEAD-TIME
DIODE EMULATION
V/I SAMPLE TIMING
PWM/HYS TRANSITION
PHASE2
PGND2
LGATE2
VCC
MODE CHANGE COMP 1
+
-
SAME STATE FOR
8 CLOCK CYCLES
REQUIRED TO CHANGE
HYSTERETIC COMPARATOR 1 - PWM OR HYS MODE
+ VHYS=15mV
1M
15.2pF
VSEN1
500k
300k
1.3pF
-
+
Σ
+ 0.9V REFERENCE
ERROR AMP 1
ISEN1 100
CURRENT
SAMPLE
OCSET1
-
+ CURRENT
SAMPLE
+ 0.9V REFERENCE
OV UV
PGOOD
VOLTS/SEC
CLAMP
- PWM1
+
POR
ENABLE
BIAS SUPPLIES
REFERENCE
FAULT LATCH
SOFT START
DDR MODE
CONTROL
OC1 DDR OC2
OV UV
PGOOD
VOLTS/SEC
CLAMP
PWM2
-
+
DUTY CYCLE RAMP GENERATOR
PWM CHANNEL PHASE CONTROL
DDR EN1 EN2 VIN CH1CH2 φ
0 11
0 24.0V
180º
4.2 < VIN < 24.0V
111
VIN to GND
90º
VCC
+
MODE CHANGE COMP 2
SAME STATE FOR
8 CLOCK CYCLES
REQUIRED TO CHANGE
PWM OR HYS MODE
-
- HYSTERETIC COMPARATOR 2
VHYS=15mV
+
15.2pF
1M
500k
1.3pF
Σ
ERROR AMP 2
-
+
300k
VSEN2
DDR=0 DDR=1
0.9V REFERENCE +
CURRENT
SAMPLE
-
+
0.9V REFERENCE +
100ISEN2
CURRENT
SAMPLE
DDR=0 OCSET2
DDR=1
1/3
OCSET1
1/32
ISEN1
- OC1
+
SAME STATE FOR
8 CLOCK CYCLES
REQUIRED TO LATCH
OVER-CURRENT FAULT
VIN
DDR
OC2
-
+
VCC
SAME STATE FOR
8 CLOCK CYCLES
REQUIRED TO LATCH
OVER-CURRENT FAULT
1/32
ISEN2
+
-
1/3
OCSET2
DDR VREF
BUFFER AMP
+
-
DDR VTT
REFERENCE

6 Page



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