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PDF ISL6223 Data sheet ( Hoja de datos )
| Número de pieza | ISL6223 | |
| Descripción | Mobile Microprocessor CORE Voltage Regulator Multi-Phase Buck PWM Controller | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
February 2003
ISL6223
FN9013
Mobile Microprocessor CORE Voltage
Regulator Multi-Phase Buck PWM
Controller
The ISL6223 multi-phase PWM control IC together with its
companion gate drivers, the HIP6601, HIP6602 or HIP6603
and Intersil MOSFETs provides a precision voltage
regulation system for advanced mobile microprocessors. A
single-stage regulator that directly converts a battery voltage
to a microprocessor core voltage can be designed when high
voltage drivers are employed. Multiphase power conversion
is a marked departure from earlier single phase converter
configurations previously employed to satisfy the ever
increasing current demands of modern microprocessors.
Multi-phase converters, by distributing the power and load
current, result in smaller and lower cost transistors with
fewer input and output capacitors. These reductions accrue
from the higher effective conversion frequency with higher
frequency ripple current due to the phase interleaving
process of this topology. For example, a two phase converter
operating at 350kHz will have a ripple frequency of 700kHz.
Moreover, greater converter bandwidth of this design results
in faster response to load transients.
Outstanding features of this controller IC include
programmable VID codes from the microprocessor that
range from 0.925V to 2.00V with a system accuracy of ±1%.
Pull up currents on these VID pins eliminates the need for
external pull up resistors. In addition “droop” compensation,
used to reduce the overshoot or undershoot of the CORE
voltage, is easily programmed with a single resistor.
Another feature of this controller IC is the PGOOD monitor
circuit which is held low until the CORE voltage increases,
during its Soft-Start sequence, to 0.9V. Overvoltage, the
CORE voltage going above 2.35V, results in the converter
shutting down and turning the lower MOSFETs ON to clamp
and protect the microprocessor. Under voltage is also
detected and results in PGOOD low if the CORE voltage falls
below 0.9V. Overcurrent protection reduces the regulator
current to less than 25% of the programmed trip value. An
external capacitor connected to the DACOUT pin and
ground slows down the transition of the DAC output to avoid
triggering the overcurrent protection when the VID code
changes. These features provide monitoring and protection
for the microprocessor and power system.
Features
• Mobile VID Compatible Multi-Phase Power Conversion
• Precision Channel Current Sharing
- Loss Less Current Sampling - Uses rDS(ON)
• Precision CORE Voltage Regulation
- ±1% System Accuracy Over Temperature
• Microprocessor Voltage Identification Input
- 5-Bit VID Input
- 1.30V to 2.00V in 50mV Steps
- 0.925V to 1.275V in 25mV Steps
- Programmable “Droop” Voltage
• Fast Transient Recovery Time
• Over Current Protection
• High Ripple Frequency (Channel Frequency Times
Number of Channels, Two). . . . . . . . . . . .100kHz to 3MHz
Ordering Information
PART NUMBER TEMP. (oC) PACKAGE PKG. NO.
ISL6223CA
0 to 70 20 Ld SSOP M20.15
ISL6223CA-T
20 Ld SSOP Tape and Reel
ISL6223EVAL1
Evaluation Platform
ISL6223EVAL2
Evaluation Platform
Pinout
ISL6223 (SSOP)
TOP VIEW
VID4 1
VID3 2
VID2 3
VID1 4
VID0 5
COMP 6
FB 7
FS/DIS 8
GND 9
VSEN 10
20 VCC
19 PGOOD
18 NC
17 NC
16 ISEN1
15 PWM1
14 PWM2
13 ISEN2
12 NC
11 DACOUT
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6223
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V
Input, Output, or I/O Voltage . . . . . . . . . . GND -0.3V to VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Recommended Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
120
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SSOP - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications Operating Conditions: VCC = 5V, TA = 0oC to 70oC, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
INPUT SUPPLY POWER
Input Supply Current
POR (Power-On Reset) Threshold
REFERENCE AND DAC
RT = 100kΩ, Active and Disabled Maximum Limit
VCC Rising
VCC Falling
-
4.25
3.75
System Accuracy
Percent System Deviation from Programmed VID Codes
-1
DAC (VID0 - VID4) Input Low Voltage
DAC Programming Input Low Threshold Voltage
-
DAC (VID0 - VID4) Input High Voltage
DAC Programming Input High Threshold Voltage
2.0
VID Pull-Up
VIDx = 0V
5
CHANNEL GENERATOR
Frequency, FSW
Adjustment Range
RT = 100kΩ, ±1%
See Figure 11
245
0.05
Disable Voltage
ERROR AMPLIFIER
Maximum Voltage at FS/DIS to Disable Controller. IFS/DIS = 1mA
-
DC Gain
Gain-Bandwidth Product
Slew Rate
Maximum Output Voltage
Minimum Output Voltage
ISEN
Full Scale Input Current
RL = 10K to GND
CL = 100pF, RL = 10K to GND
CL = 100pF, Load = ±400µA
RL = 10K to GND, Load = 400µA
RL = 10K to GND, Load = -400µA
-
-
-
3.6
-
-
Overcurrent Trip Level
60
POWER GOOD MONITOR
Undervoltage Threshold
VSEN Rising
-
VSEN Falling
-
PGOOD Low Output Voltage
PROTECTION
IPGOOD = 4mA
-
Overvoltage Threshold
VSEN Rising
2.28
VSEN Falling After Overvoltage
-
TYP
10
4.38
3.88
-
-
-
12
275
-
-
72
18
5.3
4.1
0.16
50
75
0.90
0.88
0.18
2.35
1.7
MAX UNITS
15 mA
4.5 V
4.00 V
1%
0.8 V
-V
30 µA
305 kHz
1.5 MHz
1.0 V
- dB
- MHz
- V/µs
-V
0.5 V
- µA
90 µA
-V
-V
0.4 V
2.45 V
-V
5
5 Page 
ISL6223
With a high dv/dt load transient, typical of high performance
microprocessors, the largest deviations in output voltage
occur at the leading and trailing edges of the load transient. In
order to fully utilize the output-voltage tolerance range, the
output voltage is positioned in the upper half of the range
when the output is unloaded and in the lower half of the range
when the controller is under full load. This droop
compensation allows larger transient voltage deviations and
thus reduces the size and cost of the output filter components.
RIN should be selected to give the desired “droop” voltage at
the normal full load current 50µA applied through the RISEN
resistor (or at a different full load current if adjusted as under
“Overcurrent, Selecting RISEN” above).
RIN = VDROOP / 50µA
For a VDROOP of 80mV, RIN = 1.6kΩ
The AC feedback components, RFB and Cc, are scaled in
relation to RIN.
Current Balancing
The detected currents are also used to balance the phase
currents.
Each phase’s current is compared to the average of the two
phase currents, and the difference is used to create an offset
in that phase’s PWM comparator. The offset is in a direction
to reduce the imbalance.
The balancing circuit can not make up for a difference in
rDS(ON) between synchronous rectifiers. If a FET has a
higher rDS(ON), the current through that phase will be
reduced.
Figures 9 and 10 show the inductor current of a two phase
system without and with current balancing.
Inductor Current
The inductor current in each phase of a multi-phase Buck
converter has two components. There is a current equal to
the load current divided by the number of phases (ILT / n),
and a sawtooth current (iPK-PK), resulting from switching.
The sawtooth component is dependent on the size of the
inductors, the switching frequency of each phase, and the
values of the input and output voltage. Ignoring secondary
effects, such as series resistance, the peak to peak value of
the sawtooth current can be described by:
iPK-PK = (VIN x VCORE - VCORE2) / (L x FSW x VIN)
Where: VCORE = DC value of the output or VID voltage
VIN = DC value of the input or supply voltage
L = value of the inductor
FSW = switching frequency
Example: For VCORE = 1.6V,
VIN = 12V,
L = 1.3µH,
FSW = 250kHz,
Then iPK-PK = 4.3A
11
25
20
15
10
5
0
FIGURE 9. TWO CHANNEL MULTIPHASE SYSTEM WITH CURRENT
BALANCING DISABLED
25
20
15
10
5
0
FIGURE 10. TWO CHANNEL MULTIPHASE SYSTEM WITH CURRENT
BALANCING ENABLED
The inductor, or load current, flows alternately from VIN
through Q1 and from ground through Q2. The ISL6223
samples the on-state voltage drop across each Q2 transistor
to indicate the inductor current in that phase. The voltage
drop is sampled 1/3 of a switching period, 1/FSW, after Q1 is
turned OFF and Q2 is turned on. Because of the sawtooth
current component, the sampled current is different from the
average current per phase. Neglecting secondary effects,
the sampled current (ISAMPLE) can be related to the load
current (ILT) by:
ISAMPLE = ILT / n + (VINVCORE - 3VCORE2) / (6L x FSW x VIN)
Where: ILT = total load current
n = the number of channels
Example: Using the previously given conditions, and
For ILT = 50A,
n =2
Then ISAMPLE = 25.49A
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ISL6223.PDF ] | |
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