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ISL6207 の電気的特性と機能

ISL6207のメーカーはIntersil Corporationです、この部品の機能は「High Voltage Synchronous Rectified Buck MOSFET Driver」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL6207
部品説明 High Voltage Synchronous Rectified Buck MOSFET Driver
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ISL6207 Datasheet, ISL6207 PDF,ピン配置, 機能
®
Data Sheet
July 2003
ISL6207
FN9075.4
High Voltage Synchronous Rectified Buck
MOSFET Driver
The ISL6207 is a high frequency, dual MOSFET driver,
optimized to drive two N-Channel power MOSFETs in a
synchronous-rectified buck converter topology in mobile
computing applications. This driver, combined with an Intersil
Multi-Phase Buck PWM controller, such as ISL6223, ISL6215,
and ISL6216, forms a complete single-stage core-voltage
regulator solution for advanced mobile microprocessors.
The ISL6207 features 4A typical sink current for the lower gate
driver. The 4A typical sink current is capable of holding the
lower MOSFET gate during the Phase node rising edge to
prevent the shoot-through power loss caused by the high dv/dt
of the Phase node. The operation voltage matches the 30V
breakdown voltage of the MOSFETs commonly used in mobile
computer power supplies.
The ISL6207 also features a three-state PWM input that,
working together with most of Intersil multiphase PWM
controllers, will prevent a negative transient on the output
voltage when the output is being shut down. This feature
eliminates the Schottky diode, that is usually seen in a
microprocessor power system for protecting the
microprocessor, from reversed-output-voltage damage.
The ISL6207 has the capacity to efficiently switch power
MOSFETs at frequencies up to 2MHz. Each driver is capable of
driving a 3000pF load with a 8ns propagation delay and less
than a 10ns transition time. This product implements
bootstrapping on the upper gate with an internal bootstrap
Schottky diode, reducing implementation cost, complexity, and
allowing the use of higher performance, cost effective
N-Channel MOSFETs. Adaptive shoot-through protection is
integrated to prevent both MOSFETs from conducting
simultaneously.
Ordering Information
PART #
TEMP.
RA(oNCG) E
PACKAGE
PKG.
DWG. #
ISL6207CB
-10 to 85 8 Lead SOIC
M8.15
ISL6207CB-T
8 Ld SOIC Tape & Reel
M8.15
ISL6207CR
-10 to 85 8 Lead 3x3 QFN
L8.3x3
ISL6207CR-T
8 Ld QFN Tape & Reel
L8.3x3
ISL6207CBZ -10 to 85 8 Lead SOIC (Ld Free) M8.15
ISL6207CBZ-T 8 Ld SOIC (Ld Free) Tape & Reel M8.15
ISL6207HBZ -10 to 100 8 Ld SOIC (Ld Free)
M8.15
ISL6207HBZ-T 8 Ld SOIC (Ld Free) Tape & Reel M8.15
ISL6207CRZ -10 to 85 8 Lead 3x3 QFN (Ld Free) L8.3x3
ISL6207CRZ-T 8 Lead QFN (Ld Free) Tape & Reel L8.3x3
ISL6207HRZ -10 to 100 8 Ld 3x3 QFN (Ld Free) L8.3x3
ISL6207HRZ-T 8 Lead QFN (Ld Free) Tape & Reel L8.3x3
Features
• Drives Two N-Channel MOSFETs
• Adaptive Shoot-Through Protection
• 30V Operation Voltage
• 0.4On-Resistance and 4A Sink Current Capability
• Supports High Switching Frequency
- Fast Output Rise Time
- Propagation Delay 8ns
• Three-State PWM Input for Power Stage Shutdown
• Internal Bootstrap Schottky Diode
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
Applications
• Core Voltage Supplies for Intel and AMD® Mobile
Microprocessors
• High Frequency Low Profile DC-DC Converters
• High Current Low Output Voltage DC-DC Converters
• High Input Voltage DC-DC Converters
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”
Pinouts
ISL6207 (SOIC-8)
TOP VIEW
ISL6207 (QFN)
TOP VIEW
UGATE 1
BOOT 2
PWM 3
GND 4
8 PHASE
7 EN
6 VCC
5 LGATE
BOOT 1
PWM 2
87
66 EN
5 VCC
34
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved. All other trademarks mentioned are the property of their respective ownerS.
Intel® is a registered trademark of Intel Corporation. AMD® is a registered trademark of Advanced Micro Devices, Inc.

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ISL6207 pdf, ピン配列
ISL6207
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
BOOT Voltage (VBOOT). . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 36V
Phase Voltage (VPHASE) (Note 1). . . VBOOT - 7V to VBOOT + 0.3V
Input Voltage (VEN, VPWM) . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V
UGATE. . . . . . . . . . . . . . . . . . . . . . VPHASE - 0.3V to VBOOT + 0.3V
LGATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V
Ambient Temperature Range. . . . . . . . . . . . . . . . . . -40oC to 125oC
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . -10oC to 100oC
Maximum Operating Junction Temperature. . . . . . . . . . . . . . 125oC
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
Thermal Information
Thermal Resistance (Typical Notes 3, 4, 5) θJA (oC/W) θJC (oC/W)
SOIC Package (Note 2) . . . . . . . . . . . . . . . 110
N/A
QFN Package (Notes 4, 5). . . . . . . . . . . . . . 95
36
Maximum Junction Temperature (Plastic Package) . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The Phase Voltage is capable of withstanding -7V when the BOOT pin is at GND.
2. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
VCC SUPPLY CURRENT
Bias Supply Current
Bias Supply Current
BOOTSTRAP DIODE
IVCC
IVCC
EN = LOW
PWM pin floating, VVCC = 5V
- - 5.0 µA
- 30 - µA
Forward Voltage
PWM INPUT
VF VVCC = 5V, forward bias current = 2mA
0.45 0.60 0.65
V
Input Current
PWM Three-State Rising Threshold
PWM Three-State Falling Threshold
Three-State Shutdown Holdoff Time
EN INPUT
IPWM
VPWM = 5V
VPWM = 0V
VVCC = 5V
VVCC = 5V
VVCC = 5V, temperature = 25°C
- 250 -
- -250 -
- - 1.7
3.3 -
-
- 300 -
µA
µA
V
V
ns
EN LOW Threshold
1.0 - - V
EN HIGH Threshold
- - 2.0 V
SWITCHING TIME
UGATE Rise Time
LGATE Rise Time
UGATE Fall Time
LGATE Fall Time
UGATE Turn-Off Propagation Delay
LGATE Turn-Off Propagation Delay
UGATE Turn-On Propagation Delay
LGATE Turn-On Propagation Delay
tRUGATE VVCC = 5V, 3nF Load
tRLGATE VVCC = 5V, 3nF Load
tFUGATE VVCC = 5V, 3nF Load
tFLGATE VVCC = 5V, 3nF Load
tPDLUGATE VVCC = 5V, 3nF Load
tPDLLGATE VVCC = 5V, 3nF Load
tPDHUGATE VVCC = 5V, Outputs Unloaded
tPDHLGATE VVCC = 5V, Outputs Unloaded
- 8 - ns
- 8 - ns
- 8 - ns
- 4 - ns
- 8 - ns
- 8 - ns
5 8 12 ns
5 8 12 ns
3


3Pages


ISL6207 電子部品, 半導体
ISL6207
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency and total gate charge of the selected
MOSFETs. Calculating the power dissipation in the driver for
a desired application is critical to ensuring safe operation.
Exceeding the maximum allowable power dissipation level
will push the IC beyond the maximum recommended
operating junction temperature of 125oC. The maximum
allowable IC power dissipation for the SO-8 package is
approximately 800mW. When designing the driver into an
application, it is recommended that the following calculation
be performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power dissipated
by the driver is approximated as:
P = fsw(1.5VUQU + VLQL) + IDDQVCC
where fsw is the switching frequency of the PWM signal. VU
and VL represent the upper and lower gate rail voltage. QU
and QL is the upper and lower gate charge determined by
MOSFET selection and any external capacitance added to
the gate pins. The IDDQ VCC product is the quiescent power
of the driver and is typically negligible.
6

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