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ISL6142 の電気的特性と機能

ISL6142のメーカーはIntersil Corporationです、この部品の機能は「Negative Voltage Hot Plug Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL6142
部品説明 Negative Voltage Hot Plug Controller
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ISL6142 Datasheet, ISL6142 PDF,ピン配置, 機能
ISL6142, ISL6152
®
Data Sheet
Negative Voltage Hot Plug Controller
The ISL6142/52 are 14 pin, negative voltage hot plug controllers
that allow a board to be safely inserted and removed from a live
backplane. Inrush current is limited to a programmable value by
controlling the gate voltage of an external N-channel pass
transistor. The pass transistor is turned off if the input voltage is
less than the Under-Voltage threshold, or greater than the Over-
Voltage threshold. The PWRGD/PWRGD outputs can be used to
directly enable a power module. When the Gate and DRAIN
voltages are both considered good the output is latched in the
active state.
The IntelliTripTM electronic circuit breaker and programmable
current limit features protect the system against short circuits.
When the Over-Current threshold is exceeded, the output current
is limited for a time-out period before the circuit breaker trips and
shuts down the FET. The time-out period is programmable with an
external capacitor connected to the CT pin. If the fault disappears
before the programmed time-out, normal operation resumes. In
addition, the IntelliTripTM electronic circuit breaker has a fast Hard
Fault shutdown, with a threshold set at 4 times the Over-Current
trip point. When activated, the GATE is immediately turned off and
then slowly turned back on for a single retry.
The IS+, IS-, and ISOUT pins combine to provide a load current
monitor feature that presents a scaled version of the load current
at the ISOUT pin. Current to voltage conversion is accomplished
by placing a resistor (R9) from ISOUT to the negative input (-48V).
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE PKG#
ISL6142CB
0 to 70
14 Lead SOIC M14.15
ISL6152CB
0 to 70
14 Lead SOIC M14.15
ISL6142IB
-40 to 85
14 Lead SOIC M14.15
ISL6152IB
-40 to 85
14 Lead SOIC M14.15
Related Literature
• ISL6142/52EVAL1 Board Set, Document AN1000
• ISL6140/50EVAL1 Board Set, Document AN9967
• ISL6140/41EVAL1 Board Set, Document AN1020
• ISL6141/51 Hot Plug Controller, Document FN9079
• ISL6141/51 Hot Plug Controller, Document FN9039
• ISL6116 Hot Plug Controller, Document FN4778
NOTE: See www.intersil.com/hotplug for more information.
Pinout
ISL6142 OR ISL6152 (14 LEAD SOIC)
PWRGD/PWRGD 1
FAULT 2
DIS 3
OV 4
UV 5
IS- 6
VEE 7
Top View
ISL6142/52
14 VDD
13 CT
12 ISOUT
11 DRAIN
10 GATE
9 IS+
8 SENSE
May 2002
FN9086.0
Typical Application
Logic
Supply
R10
GND
GND
FAULT
DIS
ISOUT
R4
UV
VDD
PWRGD
PWRGD
ISL6142/ISL6152
R5
OV
R6 CT VEE IS- IS+ SENSE GATE DRAIN
R3 C2
R9
C3
R7
R8
C1
R2
LOAD
CL
RL
-48V IN
R1 = 0.02(1%)
R2 = 10(5%)
R3 = 18K(5%)
R4 = 549K(1%)
R5 = 6.49K(1%)
Features
R1
R6 = 10K(1%)
R7 = R8 = 400(1%)
R9 = 4.99K(1%)
R10 = 5.1K(10%)
C1 = 150nF (25V)
Q1 -48V OUT
C2 = 3.3nF (100V)
C3 = 1500pF (25V)
Q1 = IRF530
CL = 100uF (100V)
RL = Equivalent load
• Operates from -20V to -80V (-100V Absolute Max Rating)
• Programmable Inrush Current
• Programmable Time-Out
• Programmable Current Limit
• Programmable Over-Voltage Protection
• Programmable Under-Voltage Protection
- 135 mV of hysteresis ~4.7V of hysteresis at the power supply
• VDD Under-Voltage Lock-Out (UVLO) ~ 16.5V
• IntelliTripTM Electronic Circuit Breaker distinguishes between
severe and moderate faults
- Fast shutdown for short circuit faults with a single retry (fault
current > 4X current limit value).
• FAULT pin reports the occurrence of an Over-Current Time-Out
• Disable input controls GATE shutdown and resets Over-Current
fault latch
• Load Current Monitor Function
- ISOUT provides a scaled version of the load current
- A resistor from ISOUT to -VIN provides current to voltage
conversion
• Power Good Control Output
- Output latched “good” when DRAIN and GATE voltage
thresholds are met.
- (PWRGD active low: ISL6142 (L version)
- PWRGD active high: ISL6152 (H version)
Applications
• VoIP (Voice over Internet Protocol) Servers
• Telecom systems at -48V
• Negative Power Supply Control
• +24V Wireless Base Station Power
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a registered trademark of Intersil Americas Inc.
Intellitrip™ is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002, All Rights Reserved

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ISL6142 pdf, ピン配列
ISL6142, ISL6152
Pin Descriptions
PWRGD (ISL6142; L Version) Pin 1 - This digital output is
an open-drain pull-down device and can be used to directly
enable an external module. During start-up the DRAIN and
GATE voltages are monitored with two separate comparators.
The first comparator looks at the DRAIN pin voltage
compared to the internal VPG reference (1.3V); this measures
the voltage drop across the external FET and sense resistor.
When the DRAIN to VEE voltage drop is less than 1.3V, the
first of two conditions required for the power to be considered
good are met. In addition, the GATE voltage monitored by the
second comparator must be within approximately 2.5V of its
normal operating voltage (13.6V). When both criteria are met
the PWRGD output will transition low and be latched in the
active state, enabling the external module. When this occurs
the two comparators discussed above no longer control the
output. However a third comparator continues to monitor the
DRAIN voltage, and will drive the PWRGD output inactive if
the DRAIN voltage raises more than 8V above VEE. In
addition, any of the signals that shut off the GATE (Over-
Voltage, Under-Voltage, Under-Voltage Lock-Out, Over-
Current time-out, pulling the DIS pin high, or powering down)
will reset the latch and drive the PWRGD output high to
disable the module. In this case, the output pull-down device
shuts off, and the pin becomes high impedance. Typically an
external pull-up of some kind is used to pull the pin high
(many brick regulators have a pull-up function built in).
PWRGD (ISL6152; H Version) Pin 1 - This digital output is
used to provide an active high signal to enable an external
module. The Power Good comparators are the same as
described above, but the active state of the output is
reversed (reference figure 37).
When power is considered good (both DRAIN and GATE are
normal) the output is latched in the active high state, the
DMOS device (Q3) turns on and sinks current to VEE through
a 6.2Kresistor. The base of Q2 is clamped to VEE to turn it
off. If the external pull-up current is high enough (>1mA, for
example), the voltage drop across the resistor will be large
enough to produce a logic high output and enable the external
module (in this example, 1mA x 6.2K= 6.2V).
Note that for all H versions, although this is a digital pin
functionally, the logic high level is determined by the external
pull-up device, and the power supply to which it is
connected; the IC will not clamp it below the VDD voltage.
Therefore, if the external device does not have its own
clamp, or if it would be damaged by a high voltage, an
external clamp might be necessary.
If the power good latch is reset (GATE turns off), the internal
DMOS device (Q3) is turned off, and Q2 (NPN) turns on to
clamp the output one diode drop above the DRAIN voltage
to produce a logic low, indicating power is no longer good.
FAULT Pin 2- This digital output is an open-drain, pull-down
device, referenced to VEE. It is pulled active low whenever
the Over-Current latch is set. It goes to a high impedance
state when the fault latch is reset by toggling the UV or DIS
pins. An external pull-up resistor to a logic supply (5V or
less) is required; the fault outputs of multiple IC’s can be
wire-OR’d together. If the pin is not used it should be left
open.
DIS Pin 3 - This digital input disables the FET when driven to
a logic high state. It has a weak internal pull-up device to an
internal 5V rail (10µA), so an open pin will also act as a logic
high. The input has a nominal trip point of 1.6 V while rising,
and a hysteresis of 1.0V. The threshold voltage is
referenced to VEE, and is compatible with CMOS logic
levels. A logic low will allow the GATE to turn on (assuming
the 4 other conditions described in the GATE section are
also true). The DIS pin can also be used to reset the Over-
Current latch when toggled high to low. If not used the pin
should be tied to the negative supply rail (-VIN).
OV (Over-Voltage) Pin 4 - This analog input compares the
voltage on the pin to an internal voltage reference of 1.255 V
(nominal). When the input goes above the reference the
GATE pin is immediately pulled low to shut off the external
FET. The built in 25mV hysteresis will keep the GATE off
until the OV pin drops below 1.230V (the nominal high to low
threshold). A typical application will use an external resistor
divider from VDD to -VIN to set the OV trip level. A three-
resistor divider can be used to set both OV and UV trip
points to reduce component count.
UV (Under-Voltage) Pin 5 - This analog input compares the
voltage on the pin to an internal comparator with a built in
hysteresis of 135mv. When the UV input goes below the
nominal reference voltage of 1.120V, the GATE pin is
immediately pulled low to shut off the external FET. The
GATE will remain off until the UV pin rises above a 1.255V
low to high threshold. A typical application will use an
external resistor divider from VDD to -VIN to set the UV level
as desired. A three-resistor divider can be used to set both
OV and UV trip points to reduce component count.
The UV pin is also used to reset the Over-Current latch. The
pin must be cycled below 1.120V (nominal) and then above
1.255V (nominal) to clear the latch and initiate a normal
start-up sequence.
IS- Pin 6 - This analog pin is the negative input of the current
sense circuit. A sensing resistor (R7) is connected between
this pin and the VEE side of resistor R1. The ratio of R1/R7
defines the ISENSE to ISOUT current scaling factor. If current
sensing is not used in the application, the IS- pin should be
tied directly to the IS+ pin and the node should be left
floating.
3


3Pages


ISL6142 電子部品, 半導体
ISL6142, ISL6152
Electrical Specifications
CVoDmDm=e+rc4i8aVl (,0VoECEto=
+0V Unless Otherwise Specified. All tests are over the full temperature range;
70oC) or Industrial (-40oC to 85oC). Typical specs are at 25oC. (Continued)
either
PARAMETER
SYMBOL
TEST CONDITIONS
UV Pin Hysteresis
UV Pin Input Current
OV pin
VUVHY
IINUV
VUV = VEE
OV Pin High Threshold Voltage
OV Pin Low Threshold Voltage
OV Pin Hysteresis
OV Pin Input Current
DRAIN Pin
VOVH
VOVL
VOVHY
IINOV
OV Low to High Transition
OV High to Low Transition
VOV = VEE
Power Good Threshold (Enable PWRGD/PWRGD
Output)
VPG VDRAIN - VEE
Drain Input Bias Current
DRAIN Pin Comparator Trip Point
(PWRGD/PWRGD Inactive)
IDRAIN
VDH
VDRAIN = 48V
VDRAIN - VEE > 8.0V
ISL6142 (PWRGD Pin: L Version)
PWRGD Output Low Voltage
Output Leakage
ISL6152 (PWRGD Pin: H Version)
VOL1
VOL5
IOH
(VDRAIN - VEE) < VPG; IOUT = 1mA
(VDRAIN - VEE) < VPG; IOUT = 5mA
VDRAIN = 48V, V PWRGD = 80V
PWRGD Output Low Voltage (PWRGD-DRAIN)
PWRGD Output Impedance
DIS PIN
VOL
ROUT
VDRAIN = 5V, IOUT = 1mA
(VDRAIN - VEE) < VPG
DIS Pin High Threshold Voltage
DIS Pin Low Threshold Voltage
DIS Pin Hysteresis
DIS Pin Input High Leakage
DIS Pin Input Low Current
FAULT PIN
VDISH
VDISL
VDISHY
IDISINH
IDISINL
DIS Low to High Transition
DIS High to Low Transition
DIS Hysteresis
Input Voltage = 5V
Input Voltage = 0V
FAULT Output Voltage
FAULT Output Leakage
CT PIN
VFVOL
IFIOH
I = 1.6 mA
V = 5.0V
CT Pin Charging Current
CT Pin Input Threshold
IS PINS (IS-, IS+, ISOUT)
ISOUT Error
ISOUT Error
ISOUT Offset Current
ICTINL
VCT
VCT = 0V
VSENSE = 50mV, R7 = 400, R8 = 404
VSENSE = 200mV, R7 = 400, R8 = 404
VSENSE = 0.0mV, R7 = 400, R8 = 404
Output Voltage Range (ISOUT Pin)
MIN
-
1.235
1.215
-
0.80
10
7.0
-
-
-
-
4.5
1.60
7.5
0
TYP
135
-0.05
1.255
1.230
25
-0.05
1.30
38
8.0V
0.3
1.50
0.05
0.80
6.2
2.20
1.1
1.0
0.1
10
0.4
20
8.5
2.0
1.0
4.5
5
MAX UNITS
mV
-0.5 µA
1.275
1.255
-0.5
V
V
mV
µA
2.00 V
60 µA
9.0 V
0.8 V
3.0 V
10 µA
1.0 V
7.5 k
3.00 V
1.50 V
V
1.0 µA
µA
V
10 µA
µA
9.5 V
%
%
µA
8V
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共有リンク

Link :


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Negative Voltage Hot Plug Controller

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