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PDF ISL6132 Data sheet ( Hoja de datos )
| Número de pieza | ISL6132 | |
| Descripción | Multiple Voltage Supervisory ICs | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
ISL6131, ISL6132
July 2003
FN9119
Multiple Voltage Supervisory ICs
The ISL6131 and ISL6132 are a family of high accuracy
multi voltage supervisory ICs designed to monitor voltages
greater than 0.7V in applications ranging from
microprocessors to industrial power systems. The ISL6131
is an under voltage four supply supervisor whereas the
ISL6132 is a two voltage supervisor monitoring both for
under voltage (UV) and over voltage (OV) conditions.
Both ICs feature four external resistor programmable voltage
monitoring (VMON) inputs each with a related STATUS
output that individually reports the related monitor input
condition. In addition there is a PGOOD (power good) signal
that asserts high when the STATUS outputs are in their
correct state. There is a stability delay of approximately
160ms to ensure that the monitored supply is stable before
STATUS and PGOOD are released to go high. The PGOOD
and STATUS outputs are open-drain to allow ORing of the
signals and interfacing to a wide range of logic levels.
STATUS and PGOOD outputs are guaranteed to be valid
with IC bias lower than 1V eliminating concern about
STATUS and PGOOD outputs during IC bias up and down.
VMON inputs are designed to ignore momentary transients
on the monitored supplies.
Ordering Information
PART NUMBER
TEMP.
PKG. DWG.
RANGE (oC) PACKAGE
#
ISL6131IR
-40 to +85 24 Lead QFN L24.4x4
ISL6132IR
-40 to +85 24 Lead QFN L24.4x4
ISL613XSUPEREVAL2 Evaluation Platform
Features
• Operates from 1.5V to 5.5V Supply Voltage
• Four Adjustable Voltage Monitoring Thresholds
• 150ms STATUS/PGOOD Stability Time Delay
• Four Individual Open Drain STATUS Outputs
• Guaranteed STATUS/PGOOD Valid to VDD <1V
• VDD and VMON Glitch Immunity
• VDD Lock Out
• 4mm X 4mm QFN Package
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
Applications
• Multivoltage DSPs and Processors
• µP Voltage Monitoring
• Embedded Control Systems
• Graphics Cards
• Intelligent Instruments
• Medical Equipment
• Network Routers
• Portable Battery-Powered Equipment
• Set-Top Boxes
• Telecommunications Systems
VDD
GROUND
PGOOD
EN
VMON_A
VMON_B
VMON_C
VMON_D
VDD
GROUND
PGOOD1
PGOOD2
UVMON_1
UVMON_2
OVMON_1
OVMON_2
EN1 EN2
FIGURE 1. ISL6131 TYPICAL APPLICATION USAGE
FIGURE 2. ISL6132 TYPICAL APPLICATION USAGE
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6131, ISL6132
VMONVth
VMON
INPUT
VOLTAGE
A BCD
STSDLY
STSDLY
STSDLY
STSDLY
STATUS OUTPUTS
A B CD
DC
<Tfil
>Tfil
STSDLY
C
PGOOD OUTPUT
EN INPUT
FIGURE 3. ISL6131 OPERATIONAL DIAGRAM
OVER VOLTAGE
LIMIT
UNDER VOLTAGE
LIMIT
TdelST
MONITORED VOLTAGE
RAMPING UP & DOWN
OVSTATUS
OV
<Tfil
Tfil
TdelST
Tfil
UVSTATUS
PGOOD OUTPUT
FIGURE 4. ISL6132 OPERATIONAL DIAGRAM
Typical Performance Curves
634
633
VDD = 5V
632
631
630 VDD = 1.5V
629
628
627
626
-40
-20 0 20 40 60
TEMPERATURE (oC)
FIGURE 5. UV THRESHOLD
80
100
5
0.30
0.25
0.20
0.15
0.1
0.05
-40 -20
0
20 40
60
TEMPERATURE (oC)
80
FIGURE 6. VDD CURRENT
100
5 Page 
ISL6131, ISL6132
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L24.4x4
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VGGD-2 ISSUE C)
SYMBOL
A
A1
A2
A3
b
D
D1
MILLIMETERS
MIN NOMINAL MAX
0.80 0.90 1.00
- - 0.05
- - 1.00
0.20 REF
0.18 0.23 0.30
4.00 BSC
3.75 BSC
NOTES
-
-
9
9
5, 8
-
9
D2 1.95 2.10 2.25 7, 8
E
4.00 BSC
-
E1 3.75 BSC 9
E2 1.95 2.10 2.25 7, 8
e
0.50 BSC
-
k 0.25
-
--
L 0.30 0.40 0.50 8
L1 -
- 0.15 10
N 24 2
Nd 6 3
Ne 6 3
P-
- 0.60 9
θ-
- 12 9
Rev. 2 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
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