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PDF ISL6125 Data sheet ( Hoja de datos )
| Número de pieza | ISL6125 | |
| Descripción | Power Sequencing Controllers | |
| Fabricantes | Intersil Corporation | |
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Power Sequencing Controllers
ISL6123, ISL6124, ISL6125,
ISL6126, ISL6127, ISL6128,
ISL6130
The Intersil ISL6123, ISL6124, ISL6125, ISL6126, ISL6127,
ISL6128 and ISL6130 are integrated 4-channel
controlled-on/controlled-off power-supply sequencers with
supply monitoring, fault protection and a “sequence completed”
signal (RESET). For larger systems, more than four supplies can
be sequenced by simply connecting a wire between the
SYSRESET pins of cascaded ICs. The ISL6125 uses four active
open-drain outputs to control the on/off sequencing of four
supplies. The other sequencers use a patented, micropower 7x
charge pump to drive four external low-cost NFET switch gates
above the supply rail by 5.3V. These ICs can be biased from 5V
down to 1.5V by any supply.
The 4-channel ISL6123 (ENABLE input), ISL6124 (ENABLE
input) and ISL6125 offer the designer 4-rail control when all
four rails must be in minimal compliance before turn-on and
during operation. The ISL6123 and ISL6130 have a low-power
standby mode when disabled, which is suitable for
battery-powered applications.
The ISL6125 operates like the ISL6124, but instead of
charge-pump-driven gate drive outputs, it has open-drain logic
outputs for direct interface to other circuitry.
In contrast, for the ISL6126 and ISL6130, each of the four
channels operates independently. Each GATE turns on once its
individually associated input voltage requirements are met.
The ISL6127 is a pre-programmed A-B-C-D turn-on and D-C-B-A
turn-off sequenced IC. Once all inputs are in compliance and
ENABLE is asserted, sequencing begins. Each subsequent GATE
turns on after the previous one turns on.
The ISL6128 has two groups of two channels, each with its
independent I/O. It is ideal for voltage sequencing into
redundant capability loads. All four inputs must be satisfied
before turn-on, but a single group fault is ignored by the other
group.
External resistors provide flexible voltage threshold
programming of monitored rail voltages. Delay and
sequencing are provided by external capacitors for ramp-up
and ramp-down.
Additional I/O is provided for indicating and driving the RESET
state in various configurations.
For volume applications, other programmable options and
features are available. Contact Intersil sales support with your
needs.
Features
• Enables Arbitrary Turn-on and Turn-off Sequencing of Up to Four
Power Supplies (0.7V to 5V)
• Operates From 1.5V to 5V Supply Voltage
• Supplies VDD +5.3V of Charge Pumped Gate Drive
• Adjustable Voltage Slew Rate for Each Rail
• Multiple Sequencers Can be Daisy-Chained to Sequence an
Infinite Number of Independent Supplies
• Glitch Immunity
• Undervoltage Lockout for Each Supply
• 1µA Sleep State (ISL6123, ISL6130)
• Active High (ISL6123, ISL6130) ENABLE or Low (ISL6124,
ISL6125, ISL6126, ISL6127, ISL6128) ENABLE Input
• Active Open Drain Version Available (ISL6125)
• Voltage-determined Sequence (ISL6126, ISL6130)
• Pre-programmed Sequence Available (ISL6127)
• Dual Channel Groupings (ISL6128)
• QFN Package
• Pb-free (RoHS-compliant)
Applications
• Graphics Cards
• FPGA/ASIC/Microprocessor/PowerPC Supply Sequencing
• Network Routers
• Telecommunications Systems
V1 V1OUT
V2 V2OUT
V3 V3OUT
V4 V4OUT
UVLO_A
UVLO_B
UVLO_C
UVLO_D
VDD
ENABLE
SYSRST
RESET
GROUND
FIGURE 1. TYPICAL ISL6123 APPLICATION
September 26, 2012
FN9005.12
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2001, 2003-2008, 2011, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
ISL612X and ISL6130 Variant Feature Matrix
PART
NAME
ISL6123
ISL6124
ISL6125
ISL6126
ISL6127
ISL6128
ISL6130
EN/EN
CMOS/
TTL
GATE DRIVE
OR OPEN
DRAIN
OUTPUTS
EN TTL Gate Drive
EN CMOS Gate Drive
EN CMO Open Drain
EN CMOS Gate Drive
EN CMOS Gate Drive
EN CMOS Gate Drive
EN TTL Gate Drive
REQUIRED
CONDITIONS
FOR INITIAL
START-UP
4 UVLO
1 EN
4 UVLO
1 EN
4 UVLO
1 EN
1 UVLO
1 EN
4 UVLO
1 EN
4 UVLO
2 EN
1 UVLO
1 EN
NUMBER OF
UVLO INPUTS
MONITORED
BY EACH
RESET
NUMBER OF
CHANNELS THAT
TURN OFF WHEN
ONE UVLO
FAULTS
PRESET OR
ADJUSTABLE
SEQUENCE
NUMBER OF
UVLO AND
PAIRS OF I/O
FEATURES
4 UVLO
4 Gates
Time Adjustable
On and Off
4 Monitors
with 1 I/O
Auto Restart,
Low Bias Current
Sleep
4 UVLO
4 Gates
Time Adjustable 4 Monitors Auto Restart
On and Off
with 1 I/O
4 UVLO
4 Open Drain
Time Adjustable
On and Off
4 Monitors
with 1 I/O
Auto Restart, Open
Drain Sequenced
Outputs
4 UVLO
1 Gate
Voltage
Determined ON
Time Adjustable
Off
4 Monitors Gates Independent
with 1 I/O On as UVLO Valid
4 UVLO
4 Gates
Preset
4 Monitors Auto Restart
with 1 I/O
2 UVLO
2 Gates
Preset
2 Monitors Dual Redundant
with 2 I/O Operation
4 UVLO
1 Gate
Voltage
Determined ON
Time Adjustable
Off
4 Monitors
with 1 I/O
Gates Independent
On as UVLO Valid
Low Bias Current
Sleep
5 FN9005.12
September 26, 2012
5 Page 
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Typical Performance Curves (Continued)
GATE
5VOUT
3.3VOUT
SYSRST
2V/DIV
1µs/DIV
FIGURE 8. SYSRST LOW TO OUTPUT LATCH-OFF
Using the ISL6123EVAL1Z
Platform
The ISL6123EVAL1Z platform layout illustrates the small
implementation size for a typical 4-rail sequencing application.
The platform allows evaluation of the ISL6123, ISL6124,
ISL6126, ISL6127, ISL6128 and ISL6130. See Figure 17 for
schematic and photograph of evaluation platform and Table 2
for the component listing.
Significant current loading of the GATE or capacitive loading of
the DLY_ON and OFF pins will affect functionality and
performance.
The default configuration of the ISL6123EVAL1Z circuit is built
around the following design assumptions:
1. Using the ISL6123IR.
2. The four supplies being sequenced are 5V (IN_A), 3.3V
(IN_B), 2.5V (IN_D) and 1.5V (IN_C). The UVLO levels are
~80% of nominal voltages. Resistors are chosen such that
the total resistance of each divider is ~10k. Using standard
value resistors to approximate 80% of nominal voltage
supply = 0.63V on UVLO input.
3. The desired order turn-on sequence is 5V first, then 3.3V
about 12ms later, then the 2.5V supply about 19ms later,
and lastly, the 1.5V supply about 40ms later.
4. The desired turn-off sequence is first both 1.5V and 3.3V
supplies at the same time, then the 2.5V supply about
50ms later, and lastly, the 5V supply about 72ms after that.
LED off indicates sequence has completed and RESET has
released and pulled high.
The board is shipped with the ISL6123 installed and with each
of the other released variant types loose packed. As this
sequencer family has a common function pinout for most
variants, no major modifications to the board are necessary to
evaluate the other ICs. See Figure 18 for the ISL6125-specific
evaluation board and schematic.
11
All scope shots are taken from the ISL6123EVAL1Z board.
Figures 9 and 10 illustrate the desired turn-on and turn-off
sequences, respectively. The sequencing order and delay
between voltages sequencing is set by external capacitance
values; sequences other than those illustrated can be
accomplished.
Figures 11 and 12 illustrate the timing relationships between the
EN input; the RESET, DLY and GATE outputs; and the VOUT voltage
for a single channel being turned on and off, respectively. RESET
is not shown in Figure 11 as it asserts 160ms after the last GATE
goes high.
All IC family variants share a similar function for DLY_X capacitor
charging and GATE and RESET operation. Figures 13 through 16
illustrate the principal feature and functional differences for each
of the ISL6125, ISL6126, ISL6127 and ISL6128 variants.
Figure 13 shows the ISL6125 open-drain outputs being
sequenced on and off, along with the RESET relationship, which is
similar to all other family variants.
Figure 14 illustrates the independent input feature of the
ISL6126 which, once EN is low, allows for each UVLO to be
individually satisfied and for its associated GATE to turn on. Only
when the last variable VIN is satisfied, as shown, does RESET
release, to signal all input voltages are valid.
Figure 15 shows the ISL6127 pre-programmed ABCD turn-on
and DCBA turn-off order of sequencing, with minimal
non-adjustable delay between each.
Figure 16 demonstrates the independence of the ISL6128, the
redundant 2-rail sequencer. It shows that either one of the two
groups can be turned off, and the ABCD order of restart with
capacitor programmable delay, once both EN inputs are pulled
low.
FN9005.12
September 26, 2012
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet ISL6125.PDF ] | |
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