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ISL6117 の電気的特性と機能

ISL6117のメーカーはIntersil Corporationです、この部品の機能は「Power Distribution Controllers」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL6117
部品説明 Power Distribution Controllers
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ISL6117 Datasheet, ISL6117 PDF,ピン配置, 機能
Power Distribution Controllers
ISL6115, ISL6116, ISL6117,
ISL6120
This family of fully featured hot swap power controllers
targets applications in the +2.5V to +12V range. The
ISL6115 is for +12V control, the ISL6116 for +5V, the
ISL6117 for +3.3V and the ISL6120 for +2.5V control
applications. Each has a hard wired undervoltage (UV)
monitoring and reporting threshold level approximately
80% of the aforementioned voltage.
The ISL6115 has an integrated charge pump allowing
control of up to +16V rails using an external N-Channel
MOSFET whereas the other devices utilize the +12V
bias voltage to fully enhance the N-Channel pass FET.
All ICs feature programmable overcurrent (OC)
detection, current regulation (CR) with time delay to
latch-off and soft-start.
The current regulation level is set by 2 external
resistors; RISET sets the CR Vth and the other is a low
ohmic sense element across, which the CR Vth is
developed. The CR duration is set by an external
capacitor on the CTIM pin, which is charged with a
20µA current once the CR Vth level is reached. If the
voltage on the CTIM capacitor reaches 1.9V the IC then
quickly pulls down the GATE output latching off the
pass FET.
This family although designed for high side switch
control the ISL6116, ISL6117, ISL6120 can also be
used in a low side configuration for control of much
higher voltage potentials.
Features
• HOT SWAP Single Power Distribution Control
(ISL6115 for +12V, ISL6116 for +5V, ISL6117 for
+3.3V and ISL6120 for +2.5V)
• Overcurrent Fault Isolation
• Programmable Current Regulation Level
• Programmable Current Regulation Time to
Latch-Off
• Rail-to-Rail Common Mode Input Voltage Range
(ISL6115)
• Internal Charge Pump Allows the Use of N-Channel
MOSFET for +12V Control (ISL6115)
• Undervoltage and Overcurrent Latch Indicators
• Adjustable Turn-On Ramp
• Protection During Turn-On
• Two Levels of Overcurrent Detection Provide Fast
Response to Varying Fault Conditions
• 1µs Response Time to Dead Short
• Pb-Free Available (RoHS Compliant)
Applications
• Power Distribution Control
• Hot Plug Components and Circuit
Application Circuits- High Side
Controller
Application Two - Low Side
Controller
+ LOAD
-
1
ISL6115
2 ISL6116
3
ISL6117
ISL6120
4
8
7
6
5
PWRON
PGOOD
OC
+VBUS
LOAD
ISL6116
ISL6117
ISL6120
PWRON
+12V
+V SUPPLY TO BE CONTROLLED
12V REG
OC
April 29, 2010
FN9100.7
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004-2008, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL6117 pdf, ピン配列
ISL6115, ISL6116, ISL6117, ISL6120
Pin Descriptions
PIN # SYMBOL
FUNCTION
DESCRIPTION
1 ISET Current Set
Connect to the low side of the current sense resistor through the current limiting set resistor.
This pin functions as the current limit programming pin.
2 ISEN Current Sense
Connect to the more positive end of sense resistor to measure the voltage drop across this
resistor.
3
GATE External FET Gate
Connect to the gate of the external N-Channel MOSFET. A capacitor from this node to
Drive Pin
ground sets the turn-on ramp. At turn-on this capacitor will be charged to VDD +5V
(ISL6115) and to VDD (ISL6116, ISL6117, ISL6120) by a 10µA current source.
4 VSS Chip Return
5 VDD Chip Supply
12V chip supply. This can be either connected directly to the +12V rail supplying the
switched load voltage or to a dedicated VSS +12V supply.
6 CTIM Current Limit Timing Connect a capacitor from this pin to ground. This capacitor determines the time delay
Capacitor
between an overcurrent event and chip output shutdown (current limit time-out). The
duration of current limit time-out is equal to 93kΩ x CTIM.
7 PGOOD Power Good Indicator Indicates that the voltage on the ISEN pin is satisfactory. PGOOD is driven by an open
drain N-Channel MOSFET and is pulled low when the output voltage (VISEN) is less than
the UV level for the particular IC.
8 PWRON Power-ON
PWRON is used to control and reset the chip. The chip is enabled when PWRON pin is
driven high to a maximum of 5V or is left open. Do not drive this input >5V. After a
current limit time-out, the chip is reset by a low level signal applied to this pin. This input
has 20µA pull-up capability.
3 FN9100.7
April 29, 2010


3Pages


ISL6117 電子部品, 半導体
ISL6115, ISL6116, ISL6117, ISL6120
TABLE 1. RISET PROGRAMMING RESISTOR VALUE
RISET RESISTOR
10kΩ
NOMINAL CR VTH
200mV
4.99kΩ
100mV
2.5kΩ
50mV
750Ω
15mV
NOTE: Nominal Vth = RISET x 20µA.
TABLE 2. CTIM CAPACITOR VALUE
CTIM CAPACITOR
0.022µF
NOMINAL CURRENT LIMITED
PERIOD
2ms
0.047µF
4.4ms
0.1µF
9.3ms
NOTE: Nominal time-out period = CTIM x 93kΩ.
This IC responds to a severe overcurrent load (defined
as a voltage across the sense resistor >150mV over
the OC Vth set point) by immediately driving the
N-Channel MOSFET gate to 0V in about 10µs. The gate
voltage is then slowly ramped up turning on the
N-Channel MOSFET to the programmed current
regulation level; this is the start of the time-out period.
Upon a UV condition, the PGOOD signal will pull low
when tied high through a resistor to the logic or VDD
supply. This pin is a UV fault indicator. For an OC
latch-off indication, monitor CTIM, pin 6. This pin will
rise rapidly from 1.9V to VDD once the time-out period
expires.
See Figures 12 through 16 for waveforms relevant to
text.
The IC is reset after an OC latch-off condition by a low
level on the PWRON pin and is turned on by the
PWRON pin being driven high.
Application Considerations
Design applications where the CR Vth is set extremely
low (25mV or less), there is a two-fold risk to
consider.
• There is the susceptibility to noise influencing the
absolute CR Vth value. This can be addressed with a
100pF capacitor across the RSENSE resistor.
• Due to common mode limitations of the
overcurrent comparator, the voltage on the ISET
pin must be 20mV above the IC ground either
initially (from ISET*RSET) or before CTIM reaches
time-out (from gate charge-up). If this does not
happen, the IC may incorrectly report overcurrent
fault at start-up when there is no fault. Circuits
with high load capacitance and initially low load
current are susceptible to this type of unexpected
behavior.
Do not signal nor pull-up the PWRON input to > 5V.
Exceeding 6V on this pin will cause the internal charge
pump to malfunction.
During the soft-start and the time-out delay duration
with the IC in its current limit mode, the VGS of the
6
external N-Channel MOSFET is reduced driving the
MOSFET switch into a (linear region) high rDS(ON)
state. Strike a balance between the CR limit and the
timing requirements to avoid periods when the
external N-Channel MOSFETs may be damaged or
destroyed due to excessive internal power dissipation.
Refer to the MOSFET SOA information in the
manufacturer’s data sheet.
When driving particularly large capacitive loads a
longer soft-start time to prevent current regulation
upon charging and a short CR time may offer the best
application solution relative to reliability and FET MTF.
Physical layout of RSENSE resistor is critical to
avoid the possibility of false overcurrent occurrences.
Ideally, trace routing between the RSENSE resistors
and the IC is as direct and as short as possible with
zero current in the sense lines (see Figure 1)..
CORRECT
INCORRECT
TO ISEN AND
RISET
CURRENT
SENSE RESISTOR
FIGURE 1. SENSE RESISTOR PCB LAYOUT
Using the ISL6116 as a -48V
Low Side Hot Swap Power
Controller
To supply the required VDD, it is necessary to maintain
the chip supply 10V to 16V above the -48V bus. This
may be accomplished with a suitable regulator
between the voltage rail and pin 5 (VDD). By using a
regulator, the designer may ignore the bus voltage
variations. However, a low-cost alternative is to use a
Zener diode (see Figure 2 for typical 5A load control);
this option is detailed in the following.
Note that in this configuration the PGOOD feature
(pin 7) is not operational as the ISEN pin voltage is
always < UV threshold.
See Figures 17 through 20 for waveforms relevant to
-48V and other high voltage applications.
FN9100.7
April 29, 2010

6 Page



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