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ISL5961 の電気的特性と機能

ISL5961のメーカーはIntersil Corporationです、この部品の機能は「14-Bit/ +3.3V/ 130/210MSPS/ CommLinkTM High Speed D/A Converter」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL5961
部品説明 14-Bit/ +3.3V/ 130/210MSPS/ CommLinkTM High Speed D/A Converter
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ISL5961 Datasheet, ISL5961 PDF,ピン配置, 機能
TM
Data Sheet
14-Bit, +3.3V, 130/210+MSPS,
CommLinkTM High Speed D/A Converter
The ISL5961 is a 14-bit,
130/210+MSPS (Mega Samples
Per Second), CMOS, high speed,
low power, D/A (digital to analog) converter, designed
specifically for use in high performance communication
systems such as base transceiver stations utilizing 2.5G or
3G cellular protocols.
This device complements the CommLink ISL5x61 family of
high speed converters, which include 10, 12, and 14-bit
devices.
Ordering Information
PART
NUMBER
ISL5961IB
ISL5961IA
ISL5961/2IB
ISL5961/2IA
ISL5961EVAL1
TEMP.
RANGE
(oC)
PACKAGE
PKG. CLOCK
NO. SPEED
-40 to 85 28 Ld SOIC M28.3 130MHz
-40 to 85 28 Ld TSSOP M28.173 130MHz
-40 to 85 28 Ld SOIC M28.3 210MHz
-40 to 85 28 Ld TSSOP M28.173 210MHz
25 SOIC Evaluation Platform 210MHz
Pinout
D13 (MSB) 1
D12 2
D11 3
D10 4
D9 5
D8 6
D7 7
D6 8
D5 9
D4 10
D3 11
D2 12
D1 13
D0 (LSB) 14
ISL5961
TOP VIEW
28 CLK
27 DVDD
26 DCOM
25 NC
24 AVDD
23 COMP
22 IOUTA
21 IOUTB
20 ACOM
19 NC
18 FSADJ
17 REFIO
16 REFLO
15 SLEEP
ISL5961
September 2001
File Number 6007.2
Features
• Speed Grades . . . . . . . . . . . . . . . . 130M and 210+MSPS
• Low Power . . . . . 103mW with 20mA Output at 130MSPS
• Adjustable Full Scale Output Current. . . . . 2mA to 20mA
• +3.3V Power Supply
• 3V LVCMOS Compatible Inputs
• Excellent Spurious Free Dynamic Range
(75dBc to Nyquist, fS = 130MSPS, fOUT = 10MHz)
• UMTS Adjacent Channel Power =71dB at 19.2MHz
• EDGE/GSM SFDR = 94dBc at 11MHz in 20MHz Window
• Pin compatible, 3.3V, Lower Power Replacement For The
AD9754 and HI5960
Applications
• Cellular Infrastructure - Single or Multi-Carrier: IS-136, IS-
95, GSM, EDGE, CDMA2000, WCDMA, TDS-CDMA
• BWA Infrastructure
• Medical/Test Instrumentation
• Wireless Communication Systems
• High Resolution Imaging Systems
• Arbitrary Waveform Generators
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, All Rights Reserved
CommLink™ is a trademark of Intersil Americas Inc.

1 Page





ISL5961 pdf, ピン配列
ISL5961
Pin Descriptions
PIN NO.
PIN NAME
DESCRIPTION
1-14
D13 (MSB) Through Digital Data Bit 13, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit).
D0 (LSB)
15
16
17
18
19, 25
SLEEP
REFLO
REFIO
FSADJ
NC
Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep pin
has internal 20µA active pulldown current.
Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal reference.
Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is
enabled. Use 0.F cap to ground when internal reference is enabled.
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output
Current = 32 x VFSADJ/RSET.
No Connect. These should be grounded, but can be left disconnected.
21
IOUTB
The complementary current output of the device. Full scale output current is achieved when all input bits are
set to binary 0.
22
IOUTA
Current output of the device. Full scale output current is achieved when all input bits are set to binary 1.
23
COMP
Connect 0.1µF capacitor to ACOM.
24
AVDD
Analog Supply (+2.7V to +3.6V).
20
ACOM
Connect to Analog Ground.
26
DCOM
Connect to Digital Ground.
27
DVDD
Digital Supply (+2.7V to +3.6V).
28 CLK Clock Input.
3


3Pages


ISL5961 電子部品, 半導体
ISL5961
Electrical Specifications
PARAMETER
AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued)
TA = -40oC TO 85oC
TEST CONDITIONS
MIN TYP MAX UNITS
Input Logic Current, IIH, IL
Clock Input Current, IIH, IL
Digital Input Capacitance, CIN
TIMING CHARACTERISTICS
-20 - +20 µA
-10 - +10 µA
- 5 - pF
Data Setup Time, tSU
Data Hold Time, tHLD
Propagation Delay Time, tPD
See Figure 15
See Figure 15
See Figure 15
- 1.5
- 1.5
-1
- ns
- ns
- Clock
Period
CLK Pulse Width, tPW1 , tPW2
See Figure 15 (Note 3)
POWER SUPPLY CHARACTERISTICS
2 - - ns
AVDD Power Supply
DVDD Power Supply
Analog Supply Current (IAVDD)
(Note 8)
(Note 8)
3.3V, IOUTFS = 20mA
3.3V, IOUTFS = 2mA
2.7 3.3
3.6
2.7 3.3
3.6
- 27.5 28.5
- 10
-
V
V
mA
mA
Digital Supply Current (IDVDD)
3.3V (Note 5)
3.3V (Note 6)
- 3.7 5
- 6.5 8
mA
mA
Supply Current (IAVDD) Sleep Mode
Power Dissipation
3.3V, IOUTFS = Don’t Care
3.3V, IOUTFS = 20mA (Note 5)
- 1.5
-
mA
- 103 111 mW
3.3V, IOUTFS = 20mA (Note 6)
- 110 120 mW
3.3V, IOUTFS = 2mA (Note 5)
- 45 - mW
Power Supply Rejection
Single Supply (Note 7)
-0.125 - +0.125 %FSR/V
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625µA). Ideally the
ratio should be 32.
3. Parameter guaranteed by design or characterization and not production tested.
4. Spectral measurements made with differential transformer coupled output and no external filtering. For multitone testing, the same pattern was
used at different clock rates, producing different output frequencies but at the same ratio to the clock rate.
5. Measured with the clock at 130MSPS and the output frequency at 5MHz.
6. Measured with the clock at 200MSPS and the output frequency at 20MHz.
7. See “Definition of Specifications.”
8. Recommended operation is from 3.0V to 3.6V. Operation below 3.0V is possible with some degradation in spectral performance. Reduction in
analog output current may be necessary to maintain spectral performance.
9. See Typical Performance Plots.
6

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