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PDF ISL57402IN Data sheet ( Hoja de datos )
| Número de pieza | ISL57402IN | |
| Descripción | 3V Dual 10-Bit/ 20/40/60MSPS A/D Converter with Internal Voltage Reference | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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TM
PRELIMINARY
Data Sheet
ISL5740
June 2000 File Number 4821.2
3V Dual 10-Bit, 20/40/60MSPS A/D
Converter with Internal Voltage Reference
The ISL5740 is a monolithic, dual 10-bit analog-to-digital
converter fabricated in an advanced CMOS process. It is
designed for high speed applications where integration,
bandwidth and accuracy are essential. The ISL5740
features a 9-stage pipeline architecture. The fully pipelined
architecture and an innovative input stage enable the
ISL5740 to accept a variety of input configurations, single-
ended or fully differential. Only one external clock is
necessary to drive both converters and an internal band-gap
voltage reference is provided. This allows the system
designer to realize an increased level of system integration
resulting in decreased cost and power dissipation.
The ISL5740 has excellent dynamic performance while
consuming less than 280mW power at 60MSPS. The A/D
only requires a single +3.0V power supply. Data output
latches are provided which present valid data to the output
bus with a latency of 5 clock cycles.
The ISL5740 is offered in 20MSPS, 40MSPS and 60MSPS
sampling rates.
Ordering Information
PART
NUMBER
ISL5740/2IN
TEMP.
RANGE
(oC)
PACKAGE
SAMPLIN
G RATE
PKG. NO. (MSPS)
-40 to 85 48 Ld LQFP Q48.7x7
20
ISL5740/3IN -40 to 85 48 Ld LQFP Q48.7x7
ISL5740/4IN -40 to 85 48 Ld LQFP Q48.7x7
ISL5740/6IN -40 to 85 48 Ld LQFP Q48.7x7
ISL5740 EVAL 25 Evaluation Platform
30
40
60
Features
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . .20/40/60MSPS
• 9.1 Bits at fIN = 10MHz
• Low Power at 60MSPS. . . . . . . . . . . . . . . . . . . . . .280mW
• Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 6mW
• Wide Full Power Input Bandwidth. . . . . . . . . . . . . 400MHz
• SFDR at fIN = 10MHz . . . . . . . . . . . . . . . . . . . . . . . . .70dB
• Excellent Channel-to-Channel Isolation . . . . . . . . . . .75dB
• On-Chip Sample and Hold Amplifiers
• Internal Bandgap Voltage Reference . . . . . . . . . . . . 1.25V
• Single Supply Voltage Operation . . . . . . . . . .+2.7V - 3.6V
• TTL/CMOS(3V) Digital Inputs CMOS Digital Outputs
• Offset Binary or Two’s Complement Digital Data Output
Format
• Dual 10-Bit A/D Converters on a Monolithic Chip
• Pin Compatible Upgrade to AD9288
Pinout
• Wireless Local Loop
• PSK and QAM I&Q Demodulators
• Medical Imaging and Instrumentation
• Wireless Communications Systems
• Battery Powered Instruments
Pinout
GND
IIN+
IIN-
DFS
IVRIN
VROUT
QVRIN
S1
S2
QIN-
QIN+
GND
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
ID1
ID0
GND
DVCC
GND
AVCC
AVCC
GND
DVCC
GND
QD0
QD1
3-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
1 page  
ISL5740
Absolute Maximum Ratings TA = 25oC
Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . .4V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVCC
Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC
Operating Conditions
Temperature Range
ISL5740IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
ISL5740IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AV
CL
CC = DV
= 10pF;
CC =
TA =
2+53o.C0V; ;DIi/fQfeVreRnINtia=l
1.25V;
Analog
fS = 60MSPS
Input, Unless
at 50% Duty Cycle;
Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN TYP
ACCURACY
Resolution
10 -
Integral Linearity Error, INL
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
fIN = 10MHz
fIN = 10MHz
-2
- ±0.4
Offset Error, VOS
Full Scale Error, FSE
Gain Matching
fIN = DC
fIN = DC
Full Scale (Peak-to-Peak)
-36 12
-3 1
- ±1.5
DYNAMIC CHARACTERISTICS
Minimum Conversion Rate
No Missing Codes
-1
Maximum Conversion Rate
No Missing Codes
60 -
Effective Number of Bits, ENOB
Signal to Noise and Distortion Ratio, SINAD
= R-----M-----S------NR----oM---i--sS---e---S--+--i-g--D--n--i-as---lt--o---r--t--i-o----n-
fIN = 10MHz
fIN = 10MHz
9.1 -
56.8 -
Signal to Noise Ratio, SNR
= R-R----M-M----S-S-----SN----i-og---in-s---ae---l
fIN = 10MHz
57 -
Total Harmonic Distortion, THD
2nd Harmonic Distortion
3rd Harmonic Distortion
Spurious Free Dynamic Range, SFDR
Intermodulation Distortion, IMD
I/Q Channel Crosstalk
I/Q Channel Offset Match
I/Q Channel Full Scale Error Match
Transient Response
Over-Voltage Recovery
fIN = 10MHz
fIN = 10MHz
fIN = 10MHz
fIN = 10MHz
f1 = 1MHz, f2 = 1.02MHz
(Note 2)
0.2V Overdrive (Note 2)
-70 -
--
--
70 -
--
- -75
- 10
- 10
-1
-1
MAX
-
1
±1.0
+36
3
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UNITS
Bits
LSB
LSB
LSB
%fS
%fS
MSPS
MSPS
Bits
dB
dB
dBc
dBc
dBc
dBc
dBc
dBc
LSB
LSB
Cycle
Cycle
3-5
5 Page 
ISL5740
I/QIN- = +0.5V) and will be at negative full scale when I/QIN+
is equal to VDC - 0.5V (I/QIN+ - I/QIN- = -0.5V). Sufficient
headroom must be provided such that the input voltage
never goes above +3V or below AGND. In this case, VDC
could range between 0.5V and 2.5V without a significant
change in ADC performance. The simplest way to produce
VDC is to use the I/QVRIN bias source, I/QVDC, output of
the ISL5740.
The single ended analog input can be DC coupled
(Figure 19) as long as the input is within the analog input
common mode voltage range.
VIN
VDC
I/QIN+
R
C ISL5740
VDC
I/QIN-
FIGURE 7. DC COUPLED SINGLE ENDED INPUT
The resistor, R, in Figure 19 is not absolutely necessary but
may be used as a load setting resistor. A capacitor, C,
connected from I/QIN+ to I/QIN- will help filter any high
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
A single ended source may give better overall system
performance if it is first converted to differential before
driving the ISL5740.
Operational Mode
The ISL5740 contains several operational modes including a
normal two channel operation, placing one or both channels
in standby and delaying the Q channel data 1/2 clock cycle.
The operational mode is selected via the S1 and S2 pins and
is asynchronous to either clock. When either channel is
placed in standby, the output data is stalled and not high
impedance. When recovering from standby, valid data is
available after 20 clock cycles.
The delay mode can be used to set the Q channel 180
degrees out phase of the I channel if the same clock is
driving both channels. If separate, inverted clocks are used
for the I and Q channels, this feature can be used to align the
data.
OPERATIONAL MODES
S1 S2
MODE
0 0 Standby I and Q Channels.
0 1 I channel operates normally with Q Channel in
standby mode.
1 0 I and Q Channels operating with I/Q output data in
phase.
1 1 I and Q Channels operating with Q data 180 degrees
out of phase.
Sampling Clock Requirements
The ISL5740 sampling clock input provides a standard high-
speed interface to external TTL/CMOS logic families.
In order to ensure rated performance of the ISL5740, the
duty cycle of the clock should be held at 50% ±5%. It must
also have low jitter and operate at standard TTL/CMOS
levels.
Performance of the ISL5740 will only be guaranteed at
conversion rates above 1MSPS (Typ). This ensures proper
performance of the internal dynamic circuits. Similarly, when
power is first applied to the converter, a maximum of 20
cycles at a sample rate above 1MSPS must be performed
before valid data is available.
Supply and Ground Considerations
The ISL5740 has separate analog and digital supply and
ground pins to keep digital noise out of the analog signal
path. The part should be mounted on a board that provides
separate low impedance connections for the analog and
digital supplies and grounds. For best performance, the
supplies to the ISL5740 should be driven by clean, linear
regulated supplies. The board should also have good high
frequency decoupling capacitors mounted as close as
possible to the converter. If the part is powered off a single
supply then the analog supply can be isolated by a ferrite
bead from the digital supply.
Refer to the application note “Using Intersil High Speed A/D
Converters” (AN9214) for additional considerations when
using high speed converters.
3-11
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| PDF Descargar | [ Datasheet ISL57402IN.PDF ] | |
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